Commit 3696eebd authored by Andrew Jeffery's avatar Andrew Jeffery Committed by Stephen Boyd
Browse files

clk: ast2600: Add RMII RCLK gates for all four MACs 



RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a
single gate for each MAC.

Signed-off-by: default avatarAndrew Jeffery <andrew@aj.id.au>
Link: https://lkml.kernel.org/r/20191010020725.3990-3-andrew@aj.id.au


Reviewed-by: default avatarJoel Stanley <joel@jms.id.au>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 309d673e

drivers/clk/clk-ast2600.c

+46 −1
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 


#include "clk-aspeed.h"



#define ASPEED_G6_NUM_CLKS		67

#define ASPEED_G6_NUM_CLKS		71



#define ASPEED_G6_SILICON_REV		0x004
@@ -40,6 +40,9 @@ 


#define ASPEED_G6_STRAP1		0x500



#define ASPEED_MAC12_CLK_DLY		0x340

#define ASPEED_MAC34_CLK_DLY		0x350



/* Globally visible clocks */

static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
@@ -485,6 +488,11 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev) 
		return PTR_ERR(hw);

	aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;



	/* MAC1/2 RMII 50MHz RCLK */

	hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, 50000000);

	if (IS_ERR(hw))

		return PTR_ERR(hw);



	/* MAC1/2 AHB bus clock divider */

	hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,

			scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
@@ -494,6 +502,27 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev) 
		return PTR_ERR(hw);

	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;



	/* RMII1 50MHz (RCLK) output enable */

	hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,

			scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0,

			&aspeed_g6_clk_lock);

	if (IS_ERR(hw))

		return PTR_ERR(hw);

	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;



	/* RMII2 50MHz (RCLK) output enable */

	hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,

			scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0,

			&aspeed_g6_clk_lock);

	if (IS_ERR(hw))

		return PTR_ERR(hw);

	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;



	/* MAC1/2 RMII 50MHz RCLK */

	hw = clk_hw_register_fixed_rate(dev, "mac34rclk", "hclk", 0, 50000000);

	if (IS_ERR(hw))

		return PTR_ERR(hw);



	/* MAC3/4 AHB bus clock divider */

	hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,

			scu_g6_base + 0x310, 24, 3, 0,
@@ -503,6 +532,22 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev) 
		return PTR_ERR(hw);

	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;



	/* RMII3 50MHz (RCLK) output enable */

	hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0,

			scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0,

			&aspeed_g6_clk_lock);

	if (IS_ERR(hw))

		return PTR_ERR(hw);

	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC3RCLK] = hw;



	/* RMII4 50MHz (RCLK) output enable */

	hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0,

			scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0,

			&aspeed_g6_clk_lock);

	if (IS_ERR(hw))

		return PTR_ERR(hw);

	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC4RCLK] = hw;



	/* LPC Host (LHCLK) clock divider */

	hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,

			scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,

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