Commit 7e257003 authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-of-refcount', 'clk-mmio-fixed-clock', 'clk-remove-clps',... 

Merge branches 'clk-of-refcount', 'clk-mmio-fixed-clock', 'clk-remove-clps', 'clk-socfpga-parent' and 'clk-struct-size' into clk-next

 - Various DT of_node refcount fixes
 - Support for fixed rate clks populated from an MMIO register
 - Remove clps711x driver as the board support is gone

* clk-of-refcount:
  clk: dove: fix refcount leak in dove_clk_init()
  clk: mv98dx3236: fix refcount leak in mv98dx3236_clk_init()
  clk: armada-xp: fix refcount leak in axp_clk_init()
  clk: kirkwood: fix refcount leak in kirkwood_clk_init()
  clk: armada-370: fix refcount leak in a370_clk_init()
  clk: vf610: fix refcount leak in vf610_clocks_init()
  clk: imx7d: fix refcount leak in imx7d_clocks_init()
  clk: imx6sx: fix refcount leak in imx6sx_clocks_init()
  clk: imx6q: fix refcount leak in imx6q_clocks_init()
  clk: samsung: exynos4: fix refcount leak in exynos4_get_xom()
  clk: socfpga: fix refcount leak
  clk: ti: fix refcount leak in ti_dt_clocks_register()
  clk: qoriq: fix refcount leak in clockgen_init()
  clk: highbank: fix refcount leak in hb_clk_init()

* clk-mmio-fixed-clock:
  clk: Add Fixed MMIO clock driver
  dt-bindings: clk: Add bindings for Fixed MMIO clock

* clk-remove-clps:
  clk: clps711x: Remove board support

* clk-socfpga-parent:
  clk: socfpga: Don't have get_parent for single parent ops

* clk-struct-size:
  clk: imx: imx7ulp: use struct_size() in kzalloc()
parents 5908e6b7 8d726c51 50cc4caf 31cc9e09 a30a67be 921e88a4

Documentation/devicetree/bindings/clock/fixed-mmio-clock.txt

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Binding for simple memory mapped io fixed-rate clock sources.

The driver reads a clock frequency value from a single 32-bit memory mapped

I/O register and registers it as a fixed rate clock.



It was designed for test systems, like FPGA, not for complete, finished SoCs.



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : shall be "fixed-mmio-clock".

- #clock-cells : from common clock binding; shall be set to 0.

- reg : Address and length of the clock value register set.



Optional properties:

- clock-output-names : From common clock binding.



Example:

sysclock: sysclock@fd020004 {

	#clock-cells = <0>;

	compatible = "fixed-mmio-clock";

	reg = <0xfd020004 0x4>;

};

drivers/clk/Kconfig

+6 −0
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@@ -290,6 +290,12 @@ config COMMON_CLK_BD718XX 
	  This driver supports ROHM BD71837 and ROHM BD71847

	  PMICs clock gates.



config COMMON_CLK_FIXED_MMIO

	bool "Clock driver for Memory Mapped Fixed values"

	depends on COMMON_CLK && OF

	help

	  Support for Memory Mapped IO Fixed clocks



source "drivers/clk/actions/Kconfig"

source "drivers/clk/bcm/Kconfig"

source "drivers/clk/hisilicon/Kconfig"

drivers/clk/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o 
obj-$(CONFIG_ARCH_CLPS711X)		+= clk-clps711x.o

obj-$(CONFIG_COMMON_CLK_CS2000_CP)	+= clk-cs2000-cp.o

obj-$(CONFIG_ARCH_EFM32)		+= clk-efm32gg.o

obj-$(CONFIG_COMMON_CLK_FIXED_MMIO)	+= clk-fixed-mmio.o

obj-$(CONFIG_COMMON_CLK_GEMINI)		+= clk-gemini.o

obj-$(CONFIG_COMMON_CLK_ASPEED)		+= clk-aspeed.o

obj-$(CONFIG_ARCH_HIGHBANK)		+= clk-highbank.o

drivers/clk/clk-clps711x.c

+11 −50
Original line number Diff line number Diff line
@@ -44,21 +44,21 @@ struct clps711x_clk { 
	struct clk_hw_onecell_data	clk_data;

};



static struct clps711x_clk * __init _clps711x_clk_init(void __iomem *base,

						       u32 fref)

static void __init clps711x_clk_init_dt(struct device_node *np)

{

	u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi;

	u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi, fref = 0;

	struct clps711x_clk *clps711x_clk;

	unsigned i;

	void __iomem *base;



	WARN_ON(of_property_read_u32(np, "startup-frequency", &fref));



	if (!base)

		return ERR_PTR(-ENOMEM);

	base = of_iomap(np, 0);

	BUG_ON(!base);



	clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws,

					   CLPS711X_CLK_MAX),

			       GFP_KERNEL);

	if (!clps711x_clk)

		return ERR_PTR(-ENOMEM);

	BUG_ON(!clps711x_clk);



	spin_lock_init(&clps711x_clk->lock);
@@ -137,52 +137,13 @@ static struct clps711x_clk * __init _clps711x_clk_init(void __iomem *base, 
		clk_hw_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10);

	clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] =

		clk_hw_register_fixed_rate(NULL, "tick", NULL, 0, 64);

	for (i = 0; i < CLPS711X_CLK_MAX; i++)

		if (IS_ERR(clps711x_clk->clk_data.hws[i]))

	for (tmp = 0; tmp < CLPS711X_CLK_MAX; tmp++)

		if (IS_ERR(clps711x_clk->clk_data.hws[tmp]))

			pr_err("clk %i: register failed with %ld\n",

			       i, PTR_ERR(clps711x_clk->clk_data.hws[i]));



	return clps711x_clk;

}



void __init clps711x_clk_init(void __iomem *base)

{

	struct clps711x_clk *clps711x_clk;



	clps711x_clk = _clps711x_clk_init(base, 73728000);



	BUG_ON(IS_ERR(clps711x_clk));



	/* Clocksource */

	clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1],

			    NULL, "clps711x-timer.0");

	clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2],

			    NULL, "clps711x-timer.1");



	/* Drivers */

	clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM],

			    NULL, "clps711x-pwm");

	clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_UART],

			    NULL, "clps711x-uart.0");

	clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_UART],

			    NULL, "clps711x-uart.1");

}



#ifdef CONFIG_OF

static void __init clps711x_clk_init_dt(struct device_node *np)

{

	void __iomem *base = of_iomap(np, 0);

	struct clps711x_clk *clps711x_clk;

	u32 fref = 0;



	WARN_ON(of_property_read_u32(np, "startup-frequency", &fref));



	clps711x_clk = _clps711x_clk_init(base, fref);

	BUG_ON(IS_ERR(clps711x_clk));

			       tmp, PTR_ERR(clps711x_clk->clk_data.hws[tmp]));



	clps711x_clk->clk_data.num = CLPS711X_CLK_MAX;

	of_clk_add_hw_provider(np, of_clk_hw_onecell_get,

			       &clps711x_clk->clk_data);

}

CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt);
 
#endif

drivers/clk/clk-fixed-mmio.c

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// SPDX-License-Identifier: GPL-2.0



/*

 * Memory Mapped IO Fixed clock driver

 *

 * Copyright (C) 2018 Cadence Design Systems, Inc.

 *

 * Authors:

 *	Jan Kotas <jank@cadence.com>

 */



#include <linux/clk-provider.h>

#include <linux/of_address.h>

#include <linux/module.h>

#include <linux/platform_device.h>



static struct clk_hw *fixed_mmio_clk_setup(struct device_node *node)

{

	struct clk_hw *clk;

	const char *clk_name = node->name;

	void __iomem *base;

	u32 freq;

	int ret;



	base = of_iomap(node, 0);

	if (!base) {

		pr_err("%pOFn: failed to map address\n", node);

		return ERR_PTR(-EIO);

	}



	freq = readl(base);

	iounmap(base);

	of_property_read_string(node, "clock-output-names", &clk_name);



	clk = clk_hw_register_fixed_rate(NULL, clk_name, NULL, 0, freq);

	if (IS_ERR(clk)) {

		pr_err("%pOFn: failed to register fixed rate clock\n", node);

		return clk;

	}



	ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, clk);

	if (ret) {

		pr_err("%pOFn: failed to add clock provider\n", node);

		clk_hw_unregister(clk);

		clk = ERR_PTR(ret);

	}



	return clk;

}



static void __init of_fixed_mmio_clk_setup(struct device_node *node)

{

	fixed_mmio_clk_setup(node);

}

CLK_OF_DECLARE(fixed_mmio_clk, "fixed-mmio-clock", of_fixed_mmio_clk_setup);



/**

 * This is not executed when of_fixed_mmio_clk_setup succeeded.

 */

static int of_fixed_mmio_clk_probe(struct platform_device *pdev)

{

	struct clk_hw *clk;



	clk = fixed_mmio_clk_setup(pdev->dev.of_node);

	if (IS_ERR(clk))

		return PTR_ERR(clk);



	platform_set_drvdata(pdev, clk);



	return 0;

}



static int of_fixed_mmio_clk_remove(struct platform_device *pdev)

{

	struct clk_hw *clk = platform_get_drvdata(pdev);



	of_clk_del_provider(pdev->dev.of_node);

	clk_hw_unregister_fixed_rate(clk);



	return 0;

}



static const struct of_device_id of_fixed_mmio_clk_ids[] = {

	{ .compatible = "fixed-mmio-clock" },

	{ }

};

MODULE_DEVICE_TABLE(of, of_fixed_mmio_clk_ids);



static struct platform_driver of_fixed_mmio_clk_driver = {

	.driver = {

		.name = "of_fixed_mmio_clk",

		.of_match_table = of_fixed_mmio_clk_ids,

	},

	.probe = of_fixed_mmio_clk_probe,

	.remove = of_fixed_mmio_clk_remove,

};

module_platform_driver(of_fixed_mmio_clk_driver);



MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");

MODULE_DESCRIPTION("Memory Mapped IO Fixed clock driver");

MODULE_LICENSE("GPL v2");

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