Commit 7dfd5e61 authored by Benoit Parrot's avatar Benoit Parrot Committed by Tero Kristo
Browse files

clk: ti: dra7: add vpe clkctrl data 



Add clkctrl data for VPE.

Signed-off-by: default avatarBenoit Parrot <bparrot@ti.com>
Acked-by: default avatarTony Lindgren <tony@atomide.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
parent 7054c14f

drivers/clk/ti/clk-7xx.c

+6 −0
Original line number Diff line number Diff line
@@ -164,6 +164,11 @@ static const struct omap_clkctrl_reg_data dra7_cam_clkctrl_regs[] __initconst = 
	{ 0 },

};



static const struct omap_clkctrl_reg_data dra7_vpe_clkctrl_regs[] __initconst = {

	{ DRA7_VPE_VPE_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h23x2_ck" },

	{ 0 },

};



static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {

	{ DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },

	{ DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
@@ -787,6 +792,7 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = { 
	{ 0x4a005550, dra7_ipu_clkctrl_regs },

	{ 0x4a005620, dra7_dsp2_clkctrl_regs },

	{ 0x4a005720, dra7_rtc_clkctrl_regs },

	{ 0x4a005760, dra7_vpe_clkctrl_regs },

	{ 0x4a008620, dra7_coreaon_clkctrl_regs },

	{ 0x4a008720, dra7_l3main1_clkctrl_regs },

	{ 0x4a008920, dra7_ipu2_clkctrl_regs },

include/dt-bindings/clock/dra7.h

+10 −0
Original line number Diff line number Diff line
@@ -34,6 +34,11 @@ 
#define DRA7_VIP2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)

#define DRA7_VIP3_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)



/* vpe clocks */

#define DRA7_VPE_CLKCTRL_OFFSET	0x60

#define DRA7_VPE_CLKCTRL_INDEX(offset)	((offset) - DRA7_VPE_CLKCTRL_OFFSET)

#define DRA7_VPE_CLKCTRL	DRA7_VPE_CLKCTRL_INDEX(0x64)



/* coreaon clocks */

#define DRA7_SMARTREFLEX_MPU_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)

#define DRA7_SMARTREFLEX_CORE_CLKCTRL	DRA7_CLKCTRL_INDEX(0x38)
@@ -202,6 +207,11 @@ 
#define DRA7_CAM_VIP2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)

#define DRA7_CAM_VIP3_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)



/* vpe clocks */

#define DRA7_VPE_CLKCTRL_OFFSET	0x60

#define DRA7_VPE_CLKCTRL_INDEX(offset)	((offset) - DRA7_VPE_CLKCTRL_OFFSET)

#define DRA7_VPE_VPE_CLKCTRL	DRA7_VPE_CLKCTRL_INDEX(0x64)



/* coreaon clocks */

#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)

#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL	DRA7_CLKCTRL_INDEX(0x38)

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