arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register (7cd51a5a) · Commits · 戴 / test

Enable TLB features bit in ID_AA64ISAR0 register as per ARM DDI 0487F.a specification. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by:

Will Deacon <will@kernel.org> Signed-off-by:

Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by:

Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/1589881254-10082-10-git-send-email-anshuman.khandual@arm.com Signed-off-by:

Will Deacon <will@kernel.org>

arch/arm64/include/asm/sysreg.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -601,6 +601,7 @@

		/* id_aa64isar0 */
		#define ID_AA64ISAR0_RNDR_SHIFT 60
		#define ID_AA64ISAR0_TLB_SHIFT 56
		#define ID_AA64ISAR0_TS_SHIFT 52
		#define ID_AA64ISAR0_FHM_SHIFT 48
		#define ID_AA64ISAR0_DP_SHIFT 44

arch/arm64/kernel/cpufeature.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -179,6 +179,7 @@ static bool __system_matches_cap(unsigned int n);
		*/
		static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),

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