Commit 7cd03dc7 authored by Faiz Abbas's avatar Faiz Abbas Committed by Nishanth Menon
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arm64: dts: ti: k3-j7200-main: Add support for MMC/SD controller nodes 



Add support for MMC/SD controller nodes present on TI's j7200 SoCs.

There are two nodes:
        1. sdhci0 (8 bit bus width, 200 MHz, HS200, 200 MBps)
        2. sdhci1 (4 bit bus width, 50 MHz, HS, 25 MBps)

Signed-off-by: default avatarFaiz Abbas <faiz_abbas@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Tested-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: default avatarSekhar Nori <nsekhar@ti.com>
Link: https://lore.kernel.org/r/20200924112644.11076-2-faiz_abbas@ti.com
parent 0bf33149

arch/arm64/boot/dts/ti/k3-j7200-main.dtsi

+37 −0
Original line number Diff line number Diff line
@@ -358,4 +358,41 @@ 
		clocks = <&k3_clks 193 1>;

		power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;

	};



	main_sdhci0: mmc@4f80000 {

		compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";

		reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;

		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;

		clock-names = "clk_xin", "clk_ahb";

		clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;

		ti,otap-del-sel-legacy = <0x0>;

		ti,otap-del-sel-mmc-hs = <0x0>;

		ti,otap-del-sel-ddr52 = <0x6>;

		ti,otap-del-sel-hs200 = <0x8>;

		ti,otap-del-sel-hs400 = <0x0>;

		ti,strobe-sel = <0x77>;

		ti,trm-icp = <0x8>;

		bus-width = <8>;

		mmc-ddr-1_8v;

		dma-coherent;

	};



	main_sdhci1: mmc@4fb0000 {

		compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";

		reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;

		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;

		clock-names = "clk_xin", "clk_ahb";

		clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;

		ti,otap-del-sel-legacy = <0x0>;

		ti,otap-del-sel-sd-hs = <0x0>;

		ti,otap-del-sel-sdr12 = <0xf>;

		ti,otap-del-sel-sdr25 = <0xf>;

		ti,otap-del-sel-sdr50 = <0xc>;

		ti,otap-del-sel-sdr104 = <0x5>;

		ti,otap-del-sel-ddr50 = <0xc>;

		no-1-8-v;

		dma-coherent;

	};

};

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