Commit 0bf33149 authored by Vignesh Raghavendra's avatar Vignesh Raghavendra Committed by Nishanth Menon
Browse files

arm64: dts: ti: k3-j7200-som-p0: Add HyperFlash node 



J7200 SoM has a HyperFlash connected to HyperBus memory controller. But
HyperBus is muxed with OSPI, therefore keep HyperBus node disabled.
Bootloader will detect the mux and enable the node as required.

Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Reviewed-by: default avatarSekhar Nori <nsekhar@ti.com>
Link: https://lore.kernel.org/r/20200923163150.16973-3-vigneshr@ti.com
parent 1b772656

arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi

+36 −0
Original line number Diff line number Diff line
@@ -27,3 +27,39 @@ 
		};

	};

};



&wkup_pmx0 {

	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {

		pinctrl-single,pins = <

			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */

			J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */

			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */

			J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */

			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */

			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */

			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */

			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */

			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */

			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */

			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */

			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */

			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */

		>;

	};

};



&hbmc {

	/* OSPI and HBMC are muxed inside FSS, Bootloader will enable

	 * appropriate node based on board detection

	 */

	status = "disabled";

	pinctrl-names = "default";

	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;

	ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */

		 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */



	flash@0,0 {

		compatible = "cypress,hyperflash", "cfi-flash";

		reg = <0x00 0x00 0x4000000>;

	};

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE