Commit 7cabd008 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

irqchip/gic-v3: Make gic_enable_sre an inline function 



In order for gic_enable_sre to be used by the arm64 core code,
move it to arm-gic-v3.h. As a bonus, we now also check if
system registers have been already enabled, and return early
if they have.

In all cases, the function now returns a boolean indicating if
the enabling has been successful.

Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent d271976d

drivers/irqchip/irq-gic-v3.c

+9 −23
Original line number Diff line number Diff line
@@ -171,27 +171,6 @@ static void __maybe_unused gic_write_sgi1r(u64 val) 
	asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));

}



static void gic_enable_sre(void)

{

	u64 val;



	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));

	val |= ICC_SRE_EL1_SRE;

	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));

	isb();



	/*

	 * Need to check that the SRE bit has actually been set. If

	 * not, it means that SRE is disabled at EL2. We're going to

	 * die painfully, and there is nothing we can do about it.

	 *

	 * Kindly inform the luser.

	 */

	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));

	if (!(val & ICC_SRE_EL1_SRE))

		pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");

}



static void gic_enable_redist(bool enable)

{

	void __iomem *rbase;
@@ -525,8 +504,15 @@ static int gic_populate_rdist(void) 


static void gic_cpu_sys_reg_init(void)

{

	/* Enable system registers */

	gic_enable_sre();

	/*

	 * Need to check that the SRE bit has actually been set. If

	 * not, it means that SRE is disabled at EL2. We're going to

	 * die painfully, and there is nothing we can do about it.

	 *

	 * Kindly inform the luser.

	 */

	if (!gic_enable_sre())

		pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");



	/* Set priority mask register */

	gic_write_pmr(DEFAULT_PMR_VALUE);

include/linux/irqchip/arm-gic-v3.h

+16 −0
Original line number Diff line number Diff line
@@ -398,6 +398,22 @@ static inline void gic_write_dir(u64 irq) 
	isb();

}



static inline bool gic_enable_sre(void)

{

	u64 val;



	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));

	if (val & ICC_SRE_EL1_SRE)

		return true;



	val |= ICC_SRE_EL1_SRE;

	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));

	isb();

	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));



	return !!(val & ICC_SRE_EL1_SRE);

}



struct irq_domain;

int its_cpu_init(void);

int its_init(struct device_node *node, struct rdists *rdists,

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