Commit 7c764238 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'omap-for-v5.7/ti-sysc-drop-pdata-ti81xx-signed' of... 

Merge tag 'omap-for-v5.7/ti-sysc-drop-pdata-ti81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late

Drop remaining legacy platform data for cpsw and edma

With a non-critical clock fix for dm814x ethernet, we can update ti81xx
for cpsw ethernet and edma to probe them with ti-sysc interconnect
target module driver and device tree data. And we can drop the related
remaining platform data for cpsw and edma.

* tag 'omap-for-v5.7/ti-sysc-drop-pdata-ti81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: Drop legacy platform data for ti81xx edma
  ARM: dts: Configure interconnect target module for ti816x edma
  ARM: dts: Configure interconnect target module for dm814x tptc3
  ARM: dts: Configure interconnect target module for dm814x tptc2
  ARM: dts: Configure interconnect target module for dm814x tptc1
  ARM: dts: Configure interconnect target module for dm814x tptc0
  ARM: dts: Configure interconnect target module for dm814x tpcc
  ARM: OMAP2+: Drop legacy platform data for dm814x cpsw
  ARM: dts: Configure interconnect target module for dm814x cpsw
  clk: ti: Fix dm814x clkctrl for ethernet

Link: https://lore.kernel.org/r/pull-1584575307-189595@atomide.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents e6dfccb7 0143b9fd

arch/arm/boot/dts/dm814x-clocks.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -362,4 +362,18 @@ 
			#clock-cells = <2>;

		};

	};



	alwon_ethernet_cm: alwon_ethernet_cm@15d4 {

		compatible = "ti,omap4-cm";

		reg = <0x15d4 0x4>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0x15d4 0x4>;



		alwon_ethernet_clkctrl: clk@0 {

			compatible = "ti,clkctrl";

			reg = <0 0x4>;

			#clock-cells = <2>;

		};

	};

};

arch/arm/boot/dts/dm814x.dtsi

+174 −86
Original line number Diff line number Diff line
@@ -4,6 +4,8 @@ 
 * kind, whether express or implied.

 */



#include <dt-bindings/bus/ti-sysc.h>

#include <dt-bindings/clock/dm814.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/pinctrl/dm814x.h>
@@ -519,10 +521,19 @@ 
			reg = <0x47810000 0x1000>;

		};



		edma: edma@49000000 {

		target-module@49000000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49000000 0x4>;

			reg-names = "rev";

			clocks = <&alwon_clkctrl DM814_TPCC_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49000000 0x10000>;



			edma: dma@0 {

				compatible = "ti,edma3-tpcc";

			ti,hwmods = "tpcc";

			reg =	<0x49000000 0x10000>;

				reg = <0 0x10000>;

				reg-names = "edma3_cc";

				interrupts = <12 13 14>;

				interrupt-names = "edma3_ccint", "edma3_mperr",
@@ -535,38 +546,99 @@ 


				ti,edma-memcpy-channels = <20 21>;

			};

		};



		target-module@49800000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49800000 0x4>,

			      <0x49800010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&alwon_clkctrl DM814_TPTC0_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49800000 0x100000>;



		edma_tptc0: tptc@49800000 {

			edma_tptc0: dma@0 {

				compatible = "ti,edma3-tptc";

			ti,hwmods = "tptc0";

			reg =	<0x49800000 0x100000>;

				reg = <0 0x100000>;

				interrupts = <112>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		target-module@49900000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49900000 0x4>,

			      <0x49900010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&alwon_clkctrl DM814_TPTC1_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49900000 0x100000>;



		edma_tptc1: tptc@49900000 {

			edma_tptc1: dma@0 {

				compatible = "ti,edma3-tptc";

			ti,hwmods = "tptc1";

			reg =	<0x49900000 0x100000>;

				reg = <0 0x100000>;

				interrupts = <113>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		target-module@49a00000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49a00000 0x4>,

			      <0x49a00010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&alwon_clkctrl DM814_TPTC2_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49a00000 0x100000>;



		edma_tptc2: tptc@49a00000 {

			edma_tptc2: dma@0 {

				compatible = "ti,edma3-tptc";

			ti,hwmods = "tptc2";

			reg =	<0x49a00000 0x100000>;

				reg = <0 0x100000>;

				interrupts = <114>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		edma_tptc3: tptc@49b00000 {

		target-module@49b00000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49b00000 0x4>,

			      <0x49b00010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&alwon_clkctrl DM814_TPTC3_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49b00000 0x100000>;



			edma_tptc3: dma@0 {

				compatible = "ti,edma3-tptc";

			ti,hwmods = "tptc3";

			reg =	<0x49b00000 0x100000>;

				reg = <0 0x100000>;

				interrupts = <115>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		/* See TRM "Table 1-318. L4HS Instance Summary" */

		l4hs: l4hs@4a000000 {
@@ -574,12 +646,27 @@ 
			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0 0x4a000000 0x1b4040>;

		};



		/* REVISIT: Move to live under l4hs once driver is fixed */

		mac: ethernet@4a100000 {

			target-module@100000 {

				compatible = "ti,sysc-omap4-simple", "ti,sysc";

				reg = <0x100900 0x4>,

				      <0x100908 0x4>,

				      <0x100904 0x4>;

				reg-names = "rev", "sysc", "syss";

				ti,sysc-mask = <0>;

				ti,sysc-midle = <SYSC_IDLE_FORCE>,

						<SYSC_IDLE_NO>;

				ti,sysc-sidle = <SYSC_IDLE_FORCE>,

						<SYSC_IDLE_NO>;

				ti,syss-mask = <1>;

				clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>;

				clock-names = "fck";

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0 0x100000 0x8000>;



				mac: ethernet@0 {

					compatible = "ti,cpsw";

			ti,hwmods = "cpgmac0";

					clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;

					clock-names = "fck", "cpts";

					cpdma_channels = <8>;
@@ -590,11 +677,10 @@ 
					active_slave = <0>;

					cpts_clock_mult = <0x80000000>;

					cpts_clock_shift = <29>;

			reg = <0x4a100000 0x800

			       0x4a100900 0x100>;

					reg = <0 0x800>,

					      <0x900 0x100>;

					#address-cells = <1>;

					#size-cells = <1>;

			interrupt-parent = <&intc>;

					/*

					* c0_rx_thresh_pend

					* c0_rx_pend
@@ -602,31 +688,33 @@ 
					* c0_misc_pend

					*/

					interrupts = <40 41 42 43>;

			ranges;

					ranges = <0 0 0x8000>;

					syscon = <&scm_conf>;



			davinci_mdio: mdio@4a100800 {

				compatible = "ti,davinci_mdio";

					davinci_mdio: mdio@800 {

						compatible = "ti,cpsw-mdio", "ti,davinci_mdio";

						clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>;

						clock-names = "fck";

						#address-cells = <1>;

						#size-cells = <0>;

				ti,hwmods = "davinci_mdio";

						bus_freq = <1000000>;

				reg = <0x4a100800 0x100>;

						reg = <0x800 0x100>;

					};



			cpsw_emac0: slave@4a100200 {

					cpsw_emac0: slave@200 {

						/* Filled in by U-Boot */

						mac-address = [ 00 00 00 00 00 00 ];

						phys = <&phy_gmii_sel 1>;



					};



			cpsw_emac1: slave@4a100300 {

					cpsw_emac1: slave@300 {

						/* Filled in by U-Boot */

						mac-address = [ 00 00 00 00 00 00 ];

						phys = <&phy_gmii_sel 2>;

					};

				};

			};

		};



		gpmc: gpmc@50000000 {

			compatible = "ti,am3352-gpmc";

arch/arm/boot/dts/dm816x.dtsi

+130 −18
Original line number Diff line number Diff line
@@ -4,6 +4,8 @@ 
 * kind, whether express or implied.

 */



#include <dt-bindings/bus/ti-sysc.h>

#include <dt-bindings/clock/dm816.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/pinctrl/omap.h>
@@ -138,13 +140,123 @@ 
			};

		};



		edma: edma@49000000 {

			compatible = "ti,edma3";

			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";

			reg =   <0x49000000 0x10000>,

			        <0x44e10f90 0x40>;

		target-module@49000000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49000000 0x4>;

			reg-names = "rev";

			clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49000000 0x10000>;



			edma: dma@0 {

				compatible = "ti,edma3-tpcc";

				reg = <0 0x10000>;

				reg-names = "edma3_cc";

				interrupts = <12 13 14>;

			#dma-cells = <1>;

				interrupt-names = "edma3_ccint", "edma3_mperr",

						  "edma3_ccerrint";

				dma-requests = <64>;

				#dma-cells = <2>;



				ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,

					   <&edma_tptc2 3>, <&edma_tptc3 0>;



				ti,edma-memcpy-channels = <20 21>;

			};

		};



		target-module@49800000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49800000 0x4>,

			      <0x49800010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49800000 0x100000>;



			edma_tptc0: dma@0 {

				compatible = "ti,edma3-tptc";

				reg = <0 0x100000>;

				interrupts = <112>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		target-module@49900000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49900000 0x4>,

			      <0x49900010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49900000 0x100000>;



			edma_tptc1: dma@0 {

				compatible = "ti,edma3-tptc";

				reg = <0 0x100000>;

				interrupts = <113>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		target-module@49a00000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49a00000 0x4>,

			      <0x49a00010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49a00000 0x100000>;



			edma_tptc2: dma@0 {

				compatible = "ti,edma3-tptc";

				reg = <0 0x100000>;

				interrupts = <114>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		target-module@49b00000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49b00000 0x4>,

			      <0x49b00010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49b00000 0x100000>;



			edma_tptc3: dma@0 {

				compatible = "ti,edma3-tptc";

				reg = <0 0x100000>;

				interrupts = <115>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		elm: elm@48080000 {
@@ -185,7 +297,7 @@ 
			#address-cells = <2>;

			#size-cells = <1>;

			interrupts = <100>;

			dmas = <&edma 52>;

			dmas = <&edma 52 0>;

			dma-names = "rxtx";

			gpmc,num-cs = <6>;

			gpmc,num-waitpins = <2>;
@@ -202,7 +314,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <70>;

			dmas = <&edma 58 &edma 59>;

			dmas = <&edma 58 0 &edma 59 0>;

			dma-names = "tx", "rx";

		};
@@ -213,7 +325,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <71>;

			dmas = <&edma 60 &edma 61>;

			dmas = <&edma 60 0 &edma 61 0>;

			dma-names = "tx", "rx";

		};
@@ -311,10 +423,10 @@ 
			interrupts = <65>;

			ti,spi-num-cs = <4>;

			ti,hwmods = "mcspi1";

			dmas = <&edma 16 &edma 17

				&edma 18 &edma 19

				&edma 20 &edma 21

				&edma 22 &edma 23>;

			dmas = <&edma 16 0 &edma 17 0

				&edma 18 0 &edma 19 0

				&edma 20 0 &edma 21 0

				&edma 22 0 &edma 23 0>;

			dma-names = "tx0", "rx0", "tx1", "rx1",

				    "tx2", "rx2", "tx3", "rx3";

		};
@@ -324,7 +436,7 @@ 
			reg = <0x48060000 0x11000>;

			ti,hwmods = "mmc1";

			interrupts = <64>;

			dmas = <&edma 24 &edma 25>;

			dmas = <&edma 24 0 &edma 25 0>;

			dma-names = "tx", "rx";

		};
@@ -392,7 +504,7 @@ 
			reg = <0x48020000 0x2000>;

			clock-frequency = <48000000>;

			interrupts = <72>;

			dmas = <&edma 26 &edma 27>;

			dmas = <&edma 26 0 &edma 27 0>;

			dma-names = "tx", "rx";

		};
@@ -402,7 +514,7 @@ 
			reg = <0x48022000 0x2000>;

			clock-frequency = <48000000>;

			interrupts = <73>;

			dmas = <&edma 28 &edma 29>;

			dmas = <&edma 28 0 &edma 29 0>;

			dma-names = "tx", "rx";

		};
@@ -412,7 +524,7 @@ 
			reg = <0x48024000 0x2000>;

			clock-frequency = <48000000>;

			interrupts = <74>;

			dmas = <&edma 30 &edma 31>;

			dmas = <&edma 30 0 &edma 31 0>;

			dma-names = "tx", "rx";

		};

arch/arm/boot/dts/dra62x.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -12,12 +12,12 @@ 


/* Compared to dm814x, dra62x has different offsets for Ethernet */

&mac {

	reg = <0x4a100000 0x800

		0x4a101200 0x100>;

	reg = <0 0x800>,

	      <0x1200 0x100>;

};



&davinci_mdio {

	reg = <0x4a101000 0x100>;

	reg = <0x1000 0x100>;

};



#include "dra62x-clocks.dtsi"

arch/arm/mach-omap2/omap_hwmod_81xx_data.c

+0 −231
Original line number Diff line number Diff line
@@ -129,13 +129,6 @@ static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = { 
	.flags		= HWMOD_NO_IDLEST,

};



static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {

	.name		= "l3_fast",

	.clkdm_name	= "alwon_l3_fast_clkdm",

	.class		= &l3_hwmod_class,

	.flags		= HWMOD_NO_IDLEST,

};



/*

 * L4 standard peripherals, see TRM table 1-12 for devices using this.

 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
@@ -867,62 +860,6 @@ static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = { 
	.user		= OCP_USER_MPU,

};



/* CPSW on dm814x */

static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {

	.rev_offs	= 0x0,

	.sysc_offs	= 0x8,

	.syss_offs	= 0x4,

	.sysc_flags	= SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |

			  SYSS_HAS_RESET_STATUS,

	.idlemodes	= SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |

			  MSTANDBY_NO,

	.sysc_fields	= &omap_hwmod_sysc_type3,

};



static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {

	.name		= "cpgmac0",

	.sysc		= &dm814x_cpgmac_sysc,

};



static struct omap_hwmod dm814x_cpgmac0_hwmod = {

	.name		= "cpgmac0",

	.class		= &dm814x_cpgmac0_hwmod_class,

	.clkdm_name	= "alwon_ethernet_clkdm",

	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,

	.main_clk	= "cpsw_125mhz_gclk",

	.prcm		= {

		.omap4	= {

			.clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,

			.modulemode = MODULEMODE_SWCTRL,

		},

	},

};



static struct omap_hwmod_class dm814x_mdio_hwmod_class = {

	.name		= "davinci_mdio",

};



static struct omap_hwmod dm814x_mdio_hwmod = {

	.name		= "davinci_mdio",

	.class		= &dm814x_mdio_hwmod_class,

	.clkdm_name	= "alwon_ethernet_clkdm",

	.main_clk	= "cpsw_125mhz_gclk",

};



static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {

	.master		= &dm81xx_l4_hs_hwmod,

	.slave		= &dm814x_cpgmac0_hwmod,

	.clk		= "cpsw_125mhz_gclk",

	.user		= OCP_USER_MPU,

};



static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {

	.master		= &dm814x_cpgmac0_hwmod,

	.slave		= &dm814x_mdio_hwmod,

	.user		= OCP_USER_MPU,

	.flags		= HWMOD_NO_IDLEST,

};



/* EMAC Ethernet */

static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {

	.rev_offs	= 0x0,
@@ -1321,154 +1258,6 @@ static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = { 
	.user		= OCP_USER_MPU,

};



static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {

	.name		= "tpcc",

};



static struct omap_hwmod dm81xx_tpcc_hwmod = {

	.name		= "tpcc",

	.class		= &dm81xx_tpcc_hwmod_class,

	.clkdm_name	= "alwon_l3s_clkdm",

	.main_clk	= "sysclk4_ck",

	.prcm		= {

		.omap4	= {

			.clkctrl_offs	= DM81XX_CM_ALWON_TPCC_CLKCTRL,

			.modulemode	= MODULEMODE_SWCTRL,

		},

	},

};



static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {

	.master		= &dm81xx_alwon_l3_fast_hwmod,

	.slave		= &dm81xx_tpcc_hwmod,

	.clk		= "sysclk4_ck",

	.user		= OCP_USER_MPU,

};



static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {

	.name		= "tptc0",

};



static struct omap_hwmod dm81xx_tptc0_hwmod = {

	.name		= "tptc0",

	.class		= &dm81xx_tptc0_hwmod_class,

	.clkdm_name	= "alwon_l3s_clkdm",

	.main_clk	= "sysclk4_ck",

	.prcm		= {

		.omap4	= {

			.clkctrl_offs	= DM81XX_CM_ALWON_TPTC0_CLKCTRL,

			.modulemode	= MODULEMODE_SWCTRL,

		},

	},

};



static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {

	.master		= &dm81xx_alwon_l3_fast_hwmod,

	.slave		= &dm81xx_tptc0_hwmod,

	.clk		= "sysclk4_ck",

	.user		= OCP_USER_MPU,

};



static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {

	.master		= &dm81xx_tptc0_hwmod,

	.slave		= &dm81xx_alwon_l3_fast_hwmod,

	.clk		= "sysclk4_ck",

	.user		= OCP_USER_MPU,

};



static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {

	.name		= "tptc1",

};



static struct omap_hwmod dm81xx_tptc1_hwmod = {

	.name		= "tptc1",

	.class		= &dm81xx_tptc1_hwmod_class,

	.clkdm_name	= "alwon_l3s_clkdm",

	.main_clk	= "sysclk4_ck",

	.prcm		= {

		.omap4	= {

			.clkctrl_offs	= DM81XX_CM_ALWON_TPTC1_CLKCTRL,

			.modulemode	= MODULEMODE_SWCTRL,

		},

	},

};



static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {

	.master		= &dm81xx_alwon_l3_fast_hwmod,

	.slave		= &dm81xx_tptc1_hwmod,

	.clk		= "sysclk4_ck",

	.user		= OCP_USER_MPU,

};



static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {

	.master		= &dm81xx_tptc1_hwmod,

	.slave		= &dm81xx_alwon_l3_fast_hwmod,

	.clk		= "sysclk4_ck",

	.user		= OCP_USER_MPU,

};



static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {

	.name		= "tptc2",

};



static struct omap_hwmod dm81xx_tptc2_hwmod = {

	.name		= "tptc2",

	.class		= &dm81xx_tptc2_hwmod_class,

	.clkdm_name	= "alwon_l3s_clkdm",

	.main_clk	= "sysclk4_ck",

	.prcm		= {

		.omap4	= {

			.clkctrl_offs	= DM81XX_CM_ALWON_TPTC2_CLKCTRL,

			.modulemode	= MODULEMODE_SWCTRL,

		},

	},

};



static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {

	.master		= &dm81xx_alwon_l3_fast_hwmod,

	.slave		= &dm81xx_tptc2_hwmod,

	.clk		= "sysclk4_ck",

	.user		= OCP_USER_MPU,

};



static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {

	.master		= &dm81xx_tptc2_hwmod,

	.slave		= &dm81xx_alwon_l3_fast_hwmod,

	.clk		= "sysclk4_ck",

	.user		= OCP_USER_MPU,

};



static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {

	.name		= "tptc3",

};



static struct omap_hwmod dm81xx_tptc3_hwmod = {

	.name		= "tptc3",

	.class		= &dm81xx_tptc3_hwmod_class,

	.clkdm_name	= "alwon_l3s_clkdm",

	.main_clk	= "sysclk4_ck",

	.prcm		= {

		.omap4	= {

			.clkctrl_offs	= DM81XX_CM_ALWON_TPTC3_CLKCTRL,

			.modulemode	= MODULEMODE_SWCTRL,

		},

	},

};



static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {

	.master		= &dm81xx_alwon_l3_fast_hwmod,

	.slave		= &dm81xx_tptc3_hwmod,

	.clk		= "sysclk4_ck",

	.user		= OCP_USER_MPU,

};



static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {

	.master		= &dm81xx_tptc3_hwmod,

	.slave		= &dm81xx_alwon_l3_fast_hwmod,

	.clk		= "sysclk4_ck",

	.user		= OCP_USER_MPU,

};



/*

 * REVISIT: Test and enable the following once clocks work:

 * dm81xx_l4_ls__mailbox
@@ -1499,19 +1288,8 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { 
	&dm814x_l4_ls__mmc1,

	&dm814x_l4_ls__mmc2,

	&ti81xx_l4_ls__rtc,

	&dm81xx_alwon_l3_fast__tpcc,

	&dm81xx_alwon_l3_fast__tptc0,

	&dm81xx_alwon_l3_fast__tptc1,

	&dm81xx_alwon_l3_fast__tptc2,

	&dm81xx_alwon_l3_fast__tptc3,

	&dm81xx_tptc0__alwon_l3_fast,

	&dm81xx_tptc1__alwon_l3_fast,

	&dm81xx_tptc2__alwon_l3_fast,

	&dm81xx_tptc3__alwon_l3_fast,

	&dm814x_l4_ls__timer1,

	&dm814x_l4_ls__timer2,

	&dm814x_l4_hs__cpgmac0,

	&dm814x_cpgmac0__mdio,

	&dm81xx_alwon_l3_slow__gpmc,

	&dm814x_default_l3_slow__usbss,

	&dm814x_alwon_l3_med__mmc3,
@@ -1554,15 +1332,6 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { 
	&dm81xx_emac0__mdio,

	&dm816x_l4_hs__emac1,

	&dm81xx_l4_hs__sata,

	&dm81xx_alwon_l3_fast__tpcc,

	&dm81xx_alwon_l3_fast__tptc0,

	&dm81xx_alwon_l3_fast__tptc1,

	&dm81xx_alwon_l3_fast__tptc2,

	&dm81xx_alwon_l3_fast__tptc3,

	&dm81xx_tptc0__alwon_l3_fast,

	&dm81xx_tptc1__alwon_l3_fast,

	&dm81xx_tptc2__alwon_l3_fast,

	&dm81xx_tptc3__alwon_l3_fast,

	&dm81xx_alwon_l3_slow__gpmc,

	&dm816x_default_l3_slow__usbss,

	NULL,

CRA Git | Maintained and supported by SUSTech CRA and CCSE