Commit e6dfccb7 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'omap-for-v5.7/ti-sysc-drop-pdata-signed' of... 

Merge tag 'omap-for-v5.7/ti-sysc-drop-pdata-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late

Drop legacy platform data for omaps for v5.7

This series of changes continues dropping legacy platform data for
omaps by updating devices to probe with ti-sysc interconnect target
module driver:

- Update omap4, omap5, am437x, and dra7 display subsystem (DSS)
  to probe with device tree data only

- Update am335x, am437x and dra7 to probe EDMA to probe with
  device tree data only

- Drop legacy platform data for am335x and am437x PRUSS as the
  current code just keeps the devices in reset

- Drop legacy platform data for omap4 DSP and IPU as the current
  code just keeps the devices in reset

- Configure am437x and dra7 PRU-ICSS to probe with device tree
  data

For the dropped omap4 DSP and IPU platform data, there will be patches
coming later on to configure the accelerators using the omap remoteproc
bindings so hopefully folks can actually use these devices eventually.

* tag 'omap-for-v5.7/ti-sysc-drop-pdata-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (56 commits)
  ARM: OMAP2+: Drop legacy platform data for dra7 edma
  ARM: OMAP2+: Drop legacy platform data for am3 and am4 edma
  ARM: dts: Configure interconnect target module for dra7 tptc1
  ARM: dts: Configure interconnect target module for dra7 tptc0
  ARM: dts: Configure interconnect target module for dra7 tpcc
  ARM: dts: Configure interconnect target module for am4 tptc2
  ARM: dts: Configure interconnect target module for am4 tptc1
  ARM: dts: Configure interconnect target module for am4 tptc0
  ARM: dts: Configure interconnect target module for am4 tpcc
  ARM: dts: Configure interconnect target module for am3 tptc2
  ARM: dts: Configure interconnect target module for am3 tptc1
  ARM: dts: Configure interconnect target module for am3 tptc0
  ARM: dts: Configure interconnect target module for am3 tpcc
  ARM: dts: dra7: Add PRU-ICSS interconnect target-module nodes
  ARM: dts: AM4372: Add the PRU-ICSS interconnect target-module node
  ARM: dts: AM33xx-l4: Update PRUSS interconnect target-module node
  ARM: OMAP2+: Drop legacy platform data for am437x DSS
  ARM: OMAP2+: Drop legacy platform data for dra7 DSS
  ARM: OMAP2+: Drop legacy platform data for omap5 DSS
  ARM: OMAP2+: Drop legacy platform data for omap4 dss
  ...

Link: https://lore.kernel.org/r/pull-1583858385-416921@atomide.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 98d54f81 104d56b3

Documentation/devicetree/bindings/bus/ti-sysc.txt

+1 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ Required standard properties: 
		"ti,sysc-dra7-mcasp"

		"ti,sysc-usb-host-fs"

		"ti,sysc-dra7-mcan"

		"ti,sysc-pruss"



- reg		shall have register areas implemented for the interconnect

		target module in question such as revision, sysc and syss

arch/arm/boot/dts/am33xx-l4.dtsi

+18 −3
Original line number Diff line number Diff line
@@ -759,12 +759,27 @@ 
			ranges = <0x0 0x200000 0x80000>;

		};



		target-module@300000 {			/* 0x4a300000, ap 9 04.0 */

			compatible = "ti,sysc";

			status = "disabled";

		pruss_tm: target-module@300000 {	/* 0x4a300000, ap 9 04.0 */

			compatible = "ti,sysc-pruss", "ti,sysc";

			reg = <0x326000 0x4>,

			      <0x326004 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |

					 SYSC_PRUSS_SUB_MWAIT)>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>;

			clock-names = "fck";

			resets = <&prm_per 1>;

			reset-names = "rstctrl";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x300000 0x80000>;

			status = "disabled";

		};

	};

};

arch/arm/boot/dts/am33xx.dtsi

+88 −33
Original line number Diff line number Diff line
@@ -193,10 +193,19 @@ 
			reg = <0x48200000 0x1000>;

		};



		edma: edma@49000000 {

		target-module@49000000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49000000 0x4>;

			reg-names = "rev";

			clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49000000 0x10000>;



			edma: dma@0 {

				compatible = "ti,edma3-tpcc";

			ti,hwmods = "tpcc";

			reg =	<0x49000000 0x10000>;

				reg = <0 0x10000>;

				reg-names = "edma3_cc";

				interrupts = <12 13 14>;

				interrupt-names = "edma3_ccint", "edma3_mperr",
@@ -209,30 +218,76 @@ 


				ti,edma-memcpy-channels = <20 21>;

			};

		};



		edma_tptc0: tptc@49800000 {

		target-module@49800000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49800000 0x4>,

			      <0x49800010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49800000 0x100000>;



			edma_tptc0: dma@0 {

				compatible = "ti,edma3-tptc";

			ti,hwmods = "tptc0";

			reg =	<0x49800000 0x100000>;

				reg = <0 0x100000>;

				interrupts = <112>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		edma_tptc1: tptc@49900000 {

		target-module@49900000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49900000 0x4>,

			      <0x49900010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49900000 0x100000>;



			edma_tptc1: dma@0 {

				compatible = "ti,edma3-tptc";

			ti,hwmods = "tptc1";

			reg =	<0x49900000 0x100000>;

				reg = <0 0x100000>;

				interrupts = <113>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		target-module@49a00000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49a00000 0x4>,

			      <0x49a00010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49a00000 0x100000>;



		edma_tptc2: tptc@49a00000 {

			edma_tptc2: dma@0 {

				compatible = "ti,edma3-tptc";

			ti,hwmods = "tptc2";

			reg =	<0x49a00000 0x100000>;

				reg = <0 0x100000>;

				interrupts = <114>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		target-module@47810000 {

			compatible = "ti,sysc-omap2", "ti,sysc";

arch/arm/boot/dts/am4372.dtsi

+112 −67
Original line number Diff line number Diff line
@@ -185,10 +185,19 @@ 
				&pm_sram_data>;

		};



		edma: edma@49000000 {

		target-module@49000000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49000000 0x4>;

			reg-names = "rev";

			clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49000000 0x10000>;



			edma: dma@0 {

				compatible = "ti,edma3-tpcc";

			ti,hwmods = "tpcc";

			reg =	<0x49000000 0x10000>;

				reg = <0 0x10000>;

				reg-names = "edma3_cc";

				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
@@ -203,30 +212,76 @@ 


				ti,edma-memcpy-channels = <58 59>;

			};

		};



		target-module@49800000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49800000 0x4>,

			      <0x49800010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49800000 0x100000>;



		edma_tptc0: tptc@49800000 {

			edma_tptc0: dma@0 {

				compatible = "ti,edma3-tptc";

			ti,hwmods = "tptc0";

			reg =	<0x49800000 0x100000>;

				reg = <0 0x100000>;

				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		edma_tptc1: tptc@49900000 {

		target-module@49900000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49900000 0x4>,

			      <0x49900010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49900000 0x100000>;



			edma_tptc1: dma@0 {

				compatible = "ti,edma3-tptc";

			ti,hwmods = "tptc1";

			reg =	<0x49900000 0x100000>;

				reg = <0 0x100000>;

				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		edma_tptc2: tptc@49a00000 {

		target-module@49a00000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49a00000 0x4>,

			      <0x49a00010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49a00000 0x100000>;



			edma_tptc2: dma@0 {

				compatible = "ti,edma3-tptc";

			ti,hwmods = "tptc2";

			reg =	<0x49a00000 0x100000>;

				reg = <0 0x100000>;

				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		target-module@47810000 {

			compatible = "ti,sysc-omap2", "ti,sysc";
@@ -344,6 +399,28 @@ 
			};

		};



		pruss_tm: target-module@54400000 {

			compatible = "ti,sysc-pruss", "ti,sysc";

			reg = <0x54426000 0x4>,

			      <0x54426004 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |

					 SYSC_PRUSS_SUB_MWAIT)>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;

			clock-names = "fck";

			resets = <&prm_per 1>;

			reset-names = "rstctrl";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x54400000 0x80000>;

		};



		gpmc: gpmc@50000000 {

			compatible = "ti,am3352-gpmc";

			ti,hwmods = "gpmc";
@@ -394,38 +471,6 @@ 
			};

		};



		dss: dss@4832a000 {

			compatible = "ti,omap3-dss";

			reg = <0x4832a000 0x200>;

			status = "disabled";

			ti,hwmods = "dss_core";

			clocks = <&disp_clk>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			dispc: dispc@4832a400 {

				compatible = "ti,omap3-dispc";

				reg = <0x4832a400 0x400>;

				interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;

				ti,hwmods = "dss_dispc";

				clocks = <&disp_clk>;

				clock-names = "fck";



				max-memory-bandwidth = <230000000>;

			};



			rfbi: rfbi@4832a800 {

				compatible = "ti,omap3-rfbi";

				reg = <0x4832a800 0x100>;

				ti,hwmods = "dss_rfbi";

				clocks = <&disp_clk>;

				clock-names = "fck";

				status = "disabled";

			};

		};



		ocmcram: sram@40300000 {

			compatible = "mmio-sram";

			reg = <0x40300000 0x40000>; /* 256k */

arch/arm/boot/dts/am437x-l4.dtsi

+76 −1
Original line number Diff line number Diff line
@@ -2117,7 +2117,6 @@ 


		target-module@2a000 {			/* 0x4832a000, ap 88 3c.0 */

			compatible = "ti,sysc-omap2", "ti,sysc";

			ti,hwmods = "dss_core";

			reg = <0x2a000 0x4>,

			      <0x2a010 0x4>,

			      <0x2a014 0x4>;
@@ -2135,6 +2134,82 @@ 
				 <0x00000800 0x0002a800 0x00000400>,

				 <0x00000c00 0x0002ac00 0x00000400>,

				 <0x00001000 0x0002b000 0x00001000>;



			dss: dss@0 {

				compatible = "ti,omap3-dss";

				reg = <0 0x200>;

				status = "disabled";

				clocks = <&disp_clk>;

				clock-names = "fck";

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0x00000000 0x00000000 0x00000400>,

					 <0x00000400 0x00000400 0x00000400>,

					 <0x00000800 0x00000800 0x00000400>,

					 <0x00000c00 0x00000c00 0x00000400>,

					 <0x00001000 0x00001000 0x00001000>;



				target-module@400 {

					compatible = "ti,sysc-omap2", "ti,sysc";

					reg = <0x400 0x4>,

					      <0x410 0x4>,

					      <0x414 0x4>;

					reg-names = "rev", "sysc", "syss";

					ti,sysc-sidle = <SYSC_IDLE_FORCE>,

							<SYSC_IDLE_NO>,

							<SYSC_IDLE_SMART>;

					ti,sysc-midle = <SYSC_IDLE_FORCE>,

							<SYSC_IDLE_NO>,

							<SYSC_IDLE_SMART>;

					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |

							 SYSC_OMAP2_ENAWAKEUP |

							 SYSC_OMAP2_SOFTRESET |

							 SYSC_OMAP2_AUTOIDLE)>;

					ti,syss-mask = <1>;

					clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;

					clock-names = "fck";

					#address-cells = <1>;

					#size-cells = <1>;

					ranges = <0 0x400 0x400>;



					dispc: dispc@0 {

						compatible = "ti,omap3-dispc";

						reg = <0 0x400>;

						interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;

						clocks = <&disp_clk>;

						clock-names = "fck";



						max-memory-bandwidth = <230000000>;

					};

				};



				target-module@800 {

					compatible = "ti,sysc-omap2", "ti,sysc";

					reg = <0x800 0x4>,

					      <0x810 0x4>,

					      <0x814 0x4>;

					reg-names = "rev", "sysc", "syss";

					ti,sysc-sidle = <SYSC_IDLE_FORCE>,

							<SYSC_IDLE_NO>,

							<SYSC_IDLE_SMART>;

					ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |

							 SYSC_OMAP2_AUTOIDLE)>;

					ti,syss-mask = <1>;

					clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;

					clock-names = "fck";

					#address-cells = <1>;

					#size-cells = <1>;

					ranges = <0 0x800 0x400>;



					rfbi: rfbi@0 {

						compatible = "ti,omap3-rfbi";

						reg = <0 0x100>;

						clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;

						clock-names = "fck";

						status = "disabled";

					};

				};

			};

		};



		target-module@3d000 {			/* 0x4833d000, ap 102 6e.0 */

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