drm/i915/gt: Declare gen9 has 64 mocs entries! (7c5c15df) · Commits · 戴 / test

We checked the table size against a hardcoded number of entries, and that number was excluding the special mocs registers at the end. Fixes: ("drm/i915/gt: Program mocs:63 for cache eviction on gen9") Signed-off-by:

Chris Wilson <chris@chris-wilson.co.uk> Cc: <stable@vger.kernel.org> # v4.3+ Reviewed-by:

Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201127102540.13117-1-chris@chris-wilson.co.uk (cherry picked from commit 444fbf5d7058099447c5366ba8bb60d610aeb44b) Signed-off-by:

Rodrigo Vivi <rodrigo.vivi@intel.com> [backported and updated the Fixes sha]

drivers/gpu/drm/i915/gt/intel_mocs.c

+3 −4

Original line number	Diff line number	Diff line
		@@ -59,8 +59,7 @@ struct drm_i915_mocs_table {
		#define _L3_CACHEABILITY(value) ((value) << 4)

		/* Helper defines */
		#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
		#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
		#define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */

		/* (e)LLC caching options */
		/*
		@@ -328,11 +327,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
		if (INTEL_GEN(i915) >= 12) {
		table->size = ARRAY_SIZE(tgl_mocs_table);
		table->table = tgl_mocs_table;
		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
		} else if (IS_GEN(i915, 11)) {
		table->size = ARRAY_SIZE(icl_mocs_table);
		table->table = icl_mocs_table;
		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
		} else if (IS_GEN9_BC(i915) \|\| IS_CANNONLAKE(i915)) {
		table->size = ARRAY_SIZE(skl_mocs_table);
		table->n_entries = GEN9_NUM_MOCS_ENTRIES;

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