Commit 7ba28813 authored by Peter De Schrijver's avatar Peter De Schrijver Committed by Stephen Warren
Browse files

clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE 



Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are
always functional.

Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent dd93587b

drivers/clk/tegra/clk-pll.c

+5 −0
Original line number Diff line number Diff line
@@ -108,6 +108,9 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll) 
	if (!(pll->flags & TEGRA_PLL_USE_LOCK))

		return;



	if (!(pll->flags & TEGRA_PLL_HAS_LOCK_ENABLE))

		return;



	val = pll_readl_misc(pll);

	val |= BIT(pll->params->lock_enable_bit_idx);

	pll_writel_misc(val, pll);
@@ -675,6 +678,7 @@ struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 
	struct clk *clk;



	pll_flags |= TEGRA_PLL_BYPASS;

	pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;

	pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,

			      freq_table, lock);

	if (IS_ERR(pll))
@@ -698,6 +702,7 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 
	struct clk *clk;



	pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;

	pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;

	pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,

			      freq_table, lock);

	if (IS_ERR(pll))

drivers/clk/tegra/clk.h

+2 −0
Original line number Diff line number Diff line
@@ -185,6 +185,7 @@ struct tegra_clk_pll_params { 
 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the

 *     base register.

 * TEGRA_PLL_BYPASS - PLL has bypass bit

 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring

 */

struct tegra_clk_pll {

	struct clk_hw	hw;
@@ -215,6 +216,7 @@ struct tegra_clk_pll { 
#define TEGRA_PLLE_CONFIGURE BIT(7)

#define TEGRA_PLL_LOCK_MISC BIT(8)

#define TEGRA_PLL_BYPASS BIT(9)

#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)



extern const struct clk_ops tegra_clk_pll_ops;

extern const struct clk_ops tegra_clk_plle_ops;

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