Commit 7b8c87b2 authored May 28, 2019 by Shaokun Zhang Committed by Catalin Marinas Jun 04, 2019

arm64: cacheinfo: Update cache_line_size detected from DT or PPTT



cache_line_size is derived from CTR_EL0.CWG field and is called mostly
for I/O device drivers. For some platforms like the HiSilicon Kunpeng920
server SoC, cache line sizes are different between L1/2 cache and L3
cache while L1 cache line size is 64-byte and L3 is 128-byte, but
CTR_EL0.CWG is misreporting using L1 cache line size.

We shall correct the right value which is important for I/O performance.
Let's update the cache line size if it is detected from DT or PPTT
information.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Jeremy Linton <jeremy.linton@arm.com>
Cc: Zhenfa Qiu <qiuzhenfa@hisilicon.com>
Reported-by: Zhenfa Qiu <qiuzhenfa@hisilicon.com>
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

parent 9a83c84c

arch/arm64/include/asm/cache.h

+1 −5

Original line number	Diff line number	Diff line
		@@ -91,11 +91,7 @@ static inline u32 cache_type_cwg(void)

		#define __read_mostly __attribute__((__section__(".data..read_mostly")))

		static inline int cache_line_size(void)
		{
		u32 cwg = cache_type_cwg();
		return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
		}
		int cache_line_size(void);

		/*
		* Read the effective value of CTR_EL0.

arch/arm64/kernel/cacheinfo.c

+11 −0

Original line number	Diff line number	Diff line
		@@ -28,6 +28,17 @@
		#define CLIDR_CTYPE(clidr, level) \
		(((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))

		int cache_line_size(void)
		{
		u32 cwg = cache_type_cwg();

		if (coherency_max_size != 0)
		return coherency_max_size;

		return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
		}
		EXPORT_SYMBOL_GPL(cache_line_size);

		static inline enum cache_type get_cache_type(int level)
		{
		u64 clidr;

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