drivers: base: cacheinfo: Add variable to record max cache line size (9a83c84c) · Commits · 戴 / test

Add coherency_max_size variable to record the maximum cache line size for different cache levels. If it is available, we will synchronize it as cache line size, otherwise we will use CTR_EL0.CWG reporting in cache_line_size() for arm64. Cc: "Rafael J. Wysocki" <rafael@kernel.org> Cc: Jeremy Linton <jeremy.linton@arm.com> Cc: Will Deacon <will.deacon@arm.com> Reviewed-by:

Sudeep Holla <sudeep.holla@arm.com> Reviewed-by:

Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:

Shaokun Zhang <zhangshaokun@hisilicon.com> Signed-off-by:

Catalin Marinas <catalin.marinas@arm.com>

drivers/base/cacheinfo.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -213,6 +213,8 @@ int __weak cache_setup_acpi(unsigned int cpu)
		return -ENOTSUPP;
		}

		unsigned int coherency_max_size;

		static int cache_shared_cpu_map_setup(unsigned int cpu)
		{
		struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
		@@ -251,6 +253,9 @@ static int cache_shared_cpu_map_setup(unsigned int cpu)
		cpumask_set_cpu(i, &this_leaf->shared_cpu_map);
		}
		}
		/* record the maximum cache line size */
		if (this_leaf->coherency_line_size > coherency_max_size)
		coherency_max_size = this_leaf->coherency_line_size;
		}

		return 0;

include/linux/cacheinfo.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -17,6 +17,8 @@ enum cache_type {
		CACHE_TYPE_UNIFIED = BIT(2),
		};

		extern unsigned int coherency_max_size;

		/**
		* struct cacheinfo - represent a cache leaf node
		* @id: This cache's id. It is unique among caches with the same (type, level).

Admin message