Commit 7b141abe authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Kevin Hilman
Browse files

ARM: dts: meson: add the clock inputs for the Meson timer 



The Meson Timer IP block has two clock inputs:
- clk81 for using the system clock as timebase
- xtal for a timebase with 1us, 10us, 100us and 1ms resolution

The clocksource driver does not use these yet, but it's still a good
idea to add them as this describes how the hardware actually works
internally.

Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent 523b8b31

arch/arm/boot/dts/meson.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -197,7 +197,7 @@ 
				interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;

			};



			timer@9940 {

			timer_abcde: timer@9940 {

				compatible = "amlogic,meson6-timer";

				reg = <0x9940 0x18>;

				interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,

arch/arm/boot/dts/meson6.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -88,6 +88,11 @@ 
	status = "disabled";

};



&timer_abcde {

	clocks = <&xtal>, <&clk81>;

	clock-names = "xtal", "pclk";

};



&uart_AO {

	clocks = <&xtal>, <&clk81>, <&clk81>;

	clock-names = "xtal", "pclk", "baud";

arch/arm/boot/dts/meson8.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -387,6 +387,11 @@ 
	clocks = <&clkc CLKID_CLK81>;

};



&timer_abcde {

	clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;

	clock-names = "xtal", "pclk";

};



&uart_AO {

	compatible = "amlogic,meson8-uart", "amlogic,meson-uart";

	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;

arch/arm/boot/dts/meson8b.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -370,6 +370,11 @@ 
	clock-names = "core", "clkin";

};



&timer_abcde {

	clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;

	clock-names = "xtal", "pclk";

};



&uart_AO {

	compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";

	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;

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