Commit 523b8b31 authored Nov 16, 2018 by Martin Blumenstingl Committed by Kevin Hilman Nov 28, 2018

ARM: dts: meson: add the TIMER B/C/D interrupts

The timer on Meson6/Meson8/Meson8b SoCs has four internal timer events.
For each of these a separate interrupt exists.
Pass these interrupts to allow using the timers other than TIMER A.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

parent 7e26335b

arch/arm/boot/dts/meson.dtsi

+4 −1

Original line number	Diff line number	Diff line
		@@ -200,7 +200,10 @@
		timer@9940 {
		compatible = "amlogic,meson6-timer";
		reg = <0x9940 0x18>;
		interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>;
		interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
		<GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
		<GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
		<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
		};
		};