clk: renesas: rcar-gen2: Switch Z clock to .determine_rate()

	return div_u64((u64)parent_rate * mult, 32);

}

static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,

				 unsigned long *parent_rate)

static int cpg_z_clk_determine_rate(struct clk_hw *hw,

				    struct clk_rate_request *req)

{

	unsigned long prate  = *parent_rate;

	unsigned int mult;

	unsigned long prate = req->best_parent_rate;

	unsigned int min_mult, max_mult, mult;

	if (!prate)

		prate = 1;

	min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);

	max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);

	if (max_mult < min_mult)

		return -EINVAL;

	mult = div64_ul(rate * 32ULL, prate);

	mult = clamp(mult, 1U, 32U);

	mult = div64_ul(req->rate * 32ULL, prate);

	mult = clamp(mult, min_mult, max_mult);

	return div_u64((u64)*parent_rate * mult, 32);

	req->rate = div_u64((u64)prate * mult, 32);

	return 0;

}

static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,

static const struct clk_ops cpg_z_clk_ops = {

	.recalc_rate = cpg_z_clk_recalc_rate,

	.round_rate = cpg_z_clk_round_rate,

	.determine_rate = cpg_z_clk_determine_rate,

	.set_rate = cpg_z_clk_set_rate,

};