Commit 7a6854f6 authored by Vidya Sagar's avatar Vidya Sagar Committed by Lorenzo Pieralisi
Browse files

PCI: dwc: Move config space capability search API 



Move PCIe config space capability search API to common DesignWare file
as this can be used by both host and EP mode drivers.

Signed-off-by: default avatarVidya Sagar <vidyaos@nvidia.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: default avatarThierry Reding <treding@nvidia.com>
Acked-by: default avatarGustavo Pimentel <gustavo.pimentel@synopsys.com>
parent 3924bc2f

drivers/pci/controller/dwc/pcie-designware-ep.c

+2 −35
Original line number Diff line number Diff line
@@ -40,39 +40,6 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) 
	__dw_pcie_ep_reset_bar(pci, bar, 0);

}



static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,

			      u8 cap)

{

	u8 cap_id, next_cap_ptr;

	u16 reg;



	if (!cap_ptr)

		return 0;



	reg = dw_pcie_readw_dbi(pci, cap_ptr);

	cap_id = (reg & 0x00ff);



	if (cap_id > PCI_CAP_ID_MAX)

		return 0;



	if (cap_id == cap)

		return cap_ptr;



	next_cap_ptr = (reg & 0xff00) >> 8;

	return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);

}



static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap)

{

	u8 next_cap_ptr;

	u16 reg;



	reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);

	next_cap_ptr = (reg & 0x00ff);



	return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);

}



static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,

				   struct pci_epf_header *hdr)

{
@@ -612,9 +579,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) 
		dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");

		return -ENOMEM;

	}

	ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI);

	ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);



	ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX);

	ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);



	offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);

	if (offset) {

drivers/pci/controller/dwc/pcie-designware.c

+39 −0
Original line number Diff line number Diff line
@@ -14,6 +14,45 @@ 


#include "pcie-designware.h"



/*

 * These interfaces resemble the pci_find_*capability() interfaces, but these

 * are for configuring host controllers, which are bridges *to* PCI devices but

 * are not PCI devices themselves.

 */

static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,

				  u8 cap)

{

	u8 cap_id, next_cap_ptr;

	u16 reg;



	if (!cap_ptr)

		return 0;



	reg = dw_pcie_readw_dbi(pci, cap_ptr);

	cap_id = (reg & 0x00ff);



	if (cap_id > PCI_CAP_ID_MAX)

		return 0;



	if (cap_id == cap)

		return cap_ptr;



	next_cap_ptr = (reg & 0xff00) >> 8;

	return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);

}



u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)

{

	u8 next_cap_ptr;

	u16 reg;



	reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);

	next_cap_ptr = (reg & 0x00ff);



	return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);

}

EXPORT_SYMBOL_GPL(dw_pcie_find_capability);



int dw_pcie_read(void __iomem *addr, int size, u32 *val)

{

	if (!IS_ALIGNED((uintptr_t)addr, size)) {

drivers/pci/controller/dwc/pcie-designware.h

+2 −0
Original line number Diff line number Diff line
@@ -251,6 +251,8 @@ struct dw_pcie { 
#define to_dw_pcie_from_ep(endpoint)   \

		container_of((endpoint), struct dw_pcie, ep)



u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);



int dw_pcie_read(void __iomem *addr, int size, u32 *val);

int dw_pcie_write(void __iomem *addr, int size, u32 val);

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