PCI: dwc: Group DBI registers writes requiring unlocking (3924bc2f) · Commits · 戴 / test

Some of DesignWare core's DBI registers (a.k.a configuration space registers) are write-protected with a lock without enabling which they are read-only by default. These write-protected registers are implementation specific. Tegra194's BAR-0 register which is at offset 0x10 in the configuration space is an example. Current implementation in dw_pcie_setup_rc() API attempts to unlock those write-protected registers whenever they are updated and lock them back again for writing. Group all write-protected registers writes so that locking and unlocking is performed once to avoid bloating the code with multiple unlock/lock sequences for all those write-protected registers. Signed-off-by:

Vidya Sagar <vidyas@nvidia.com> Signed-off-by:

Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by:

Thierry Reding <treding@nvidia.com> Acked-by:

Jingoo Han <jingoohan1@gmail.com>

drivers/pci/controller/dwc/pcie-designware-host.c

+8 −6

Original line number	Diff line number	Diff line
		@@ -628,6 +628,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
		u32 val, ctrl, num_ctrls;
		struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

		/*
		* Enable DBI read-only registers for writing/updating configuration.
		* Write permission gets disabled towards the end of this function.
		*/
		dw_pcie_dbi_ro_wr_en(pci);

		dw_pcie_setup(pci);

		if (!pp->ops->msi_host_init) {
		@@ -650,12 +656,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
		dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);

		/* Setup interrupt pins */
		dw_pcie_dbi_ro_wr_en(pci);
		val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
		val &= 0xffff00ff;
		val \|= 0x00000100;
		dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
		dw_pcie_dbi_ro_wr_dis(pci);

		/* Setup bus numbers */
		val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
		@@ -687,15 +691,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp)

		dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);

		/* Enable write permission for the DBI read-only register */
		dw_pcie_dbi_ro_wr_en(pci);
		/* Program correct class for RC */
		dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
		/* Better disable write permission right after the update */
		dw_pcie_dbi_ro_wr_dis(pci);

		dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
		val \|= PORT_LOGIC_SPEED_CHANGE;
		dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);

		dw_pcie_dbi_ro_wr_dis(pci);
		}
		EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);

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