Commit 792592e7 authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson
Browse files

drm/i915: Move the engine mask to intel_gt_info 



Since the engines belong to the GT, move the runtime-updated list of
available engines to the intel_gt struct. The original mask has been
renamed to indicate it contains the maximum engine list that can be
found on a matching device.

In preparation for other info being moved to the gt in follow up patches
(sseu), introduce an intel_gt_info structure to group all gt-related
runtime info.

v2: s/max_engine_mask/platform_engine_mask (tvrtko), fix selftest

Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> #v1
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200708003952.21831-5-daniele.ceraolospurio@intel.com
parent f6beb381

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

+1 −2
Original line number Diff line number Diff line
@@ -1980,8 +1980,7 @@ static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch) 


static int num_vcs_engines(const struct drm_i915_private *i915)

{

	return hweight64(INTEL_INFO(i915)->engine_mask &

			 GENMASK_ULL(VCS0 + I915_MAX_VCS - 1, VCS0));

	return hweight64(VDBOX_MASK(&i915->gt));

}



/*

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+7 −6
Original line number Diff line number Diff line
@@ -370,7 +370,7 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine) 
		 * instances.

		 */

		if ((INTEL_GEN(i915) >= 11 &&

		     RUNTIME_INFO(i915)->vdbox_sfc_access & engine->mask) ||

		     engine->gt->info.vdbox_sfc_access & engine->mask) ||

		    (INTEL_GEN(i915) >= 9 && engine->instance == 0))

			engine->uabi_capabilities |=

				I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
@@ -463,7 +463,7 @@ void intel_engines_free(struct intel_gt *gt) 
static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)

{

	struct drm_i915_private *i915 = gt->i915;

	struct intel_device_info *info = mkwrite_device_info(i915);

	struct intel_gt_info *info = &gt->info;

	struct intel_uncore *uncore = gt->uncore;

	unsigned int logical_vdbox = 0;

	unsigned int i;
@@ -471,6 +471,8 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) 
	u16 vdbox_mask;

	u16 vebox_mask;



	info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;



	if (INTEL_GEN(i915) < 11)

		return info->engine_mask;
@@ -498,7 +500,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) 
		 * In TGL each VDBOX has access to an SFC.

		 */

		if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)

			RUNTIME_INFO(i915)->vdbox_sfc_access |= BIT(i);

			gt->info.vdbox_sfc_access |= BIT(i);

	}

	drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",

		vdbox_mask, VDBOX_MASK(gt));
@@ -531,7 +533,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) 
int intel_engines_init_mmio(struct intel_gt *gt)

{

	struct drm_i915_private *i915 = gt->i915;

	struct intel_device_info *device_info = mkwrite_device_info(i915);

	const unsigned int engine_mask = init_engine_mask(gt);

	unsigned int mask = 0;

	unsigned int i;
@@ -561,9 +562,9 @@ int intel_engines_init_mmio(struct intel_gt *gt) 
	 * engines.

	 */

	if (drm_WARN_ON(&i915->drm, mask != engine_mask))

		device_info->engine_mask = mask;

		gt->info.engine_mask = mask;



	RUNTIME_INFO(i915)->num_engines = hweight32(mask);

	gt->info.num_engines = hweight32(mask);



	intel_gt_check_and_clear_faults(gt);

drivers/gpu/drm/i915/gt/intel_gt.c

+6 −0
Original line number Diff line number Diff line
@@ -642,3 +642,9 @@ void intel_gt_driver_late_release(struct intel_gt *gt) 
	intel_gt_fini_timelines(gt);

	intel_engines_free(gt);

}



void intel_gt_info_print(const struct intel_gt_info *info,

			 struct drm_printer *p)

{

	drm_printf(p, "available engines: %x\n", info->engine_mask);

}

drivers/gpu/drm/i915/gt/intel_gt.h

+4 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include "intel_reset.h"



struct drm_i915_private;

struct drm_printer;



#define GT_TRACE(gt, fmt, ...) do {					\

	const struct intel_gt *gt__ __maybe_unused = (gt);		\
@@ -72,4 +73,7 @@ static inline bool intel_gt_is_wedged(const struct intel_gt *gt) 
	return unlikely(test_bit(I915_WEDGED, &gt->reset.flags));

}



void intel_gt_info_print(const struct intel_gt_info *info,

			 struct drm_printer *p);



#endif /* __INTEL_GT_H__ */

drivers/gpu/drm/i915/gt/intel_gt_types.h

+8 −0
Original line number Diff line number Diff line
@@ -109,6 +109,14 @@ struct intel_gt { 
	struct intel_gt_buffer_pool buffer_pool;



	struct i915_vma *scratch;



	struct intel_gt_info {

		intel_engine_mask_t engine_mask;

		u8 num_engines;



		/* Media engine access to SFC per instance */

		u8 vdbox_sfc_access;

	} info;

};



enum intel_gt_scratch_field {

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