Commit 78ca1108 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/book3s32: Reorder _PAGE_XXX flags to simplify TLB handling 



For pages without _PAGE_USER, PP field is 00
For pages with _PAGE_USER, PP field is 10 for RW and 11 for RO.

This patch sets _PAGE_USER to 0x002 and _PAGE_RW to 0x001
is order to simplify TLB handling by reducing amount of shifts.

The location of _PAGE_PRESENT and _PAGE_HASHPTE doesn't matter
as they are only SW related flags.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 84de6ab0

arch/powerpc/include/asm/book3s/32/hash.h

+4 −4
Original line number Diff line number Diff line
@@ -17,9 +17,9 @@ 
 * updating the accessed and modified bits in the page table tree.

 */



#define _PAGE_PRESENT	0x001	/* software: pte contains a translation */

#define _PAGE_HASHPTE	0x002	/* hash_page has made an HPTE for this pte */

#define _PAGE_USER	0x004	/* usermode access allowed */

#define _PAGE_RW	0x001	/* PP = x1: user write access allowed */

#define _PAGE_USER	0x002	/* PP = 1x: usermode access allowed */

#define _PAGE_HASHPTE	0x004	/* software: hash_page has made an HPTE for this pte */

#define _PAGE_GUARDED	0x008	/* G: prohibit speculative access */

#define _PAGE_COHERENT	0x010	/* M: enforce memory coherence (SMP systems) */

#define _PAGE_NO_CACHE	0x020	/* I: cache inhibit */
@@ -27,7 +27,7 @@ 
#define _PAGE_DIRTY	0x080	/* C: page changed */

#define _PAGE_ACCESSED	0x100	/* R: page referenced */

#define _PAGE_EXEC	0x200	/* software: exec allowed */

#define _PAGE_RW	0x400	/* software: user write access allowed */

#define _PAGE_PRESENT	0x400	/* software: pte contains a translation */

#define _PAGE_SPECIAL	0x800	/* software: Special page */



#ifdef CONFIG_PTE_64BIT

arch/powerpc/kernel/head_32.S

+1 −4
Original line number Diff line number Diff line
@@ -522,7 +522,6 @@ InstructionTLBMiss: 
	andc.	r1,r1,r0		/* check access & ~permission */

	bne-	InstructionAddressInvalid /* return if access not permitted */

	/* Convert linux-style PTE to low word of PPC-style PTE */

	rlwimi	r0,r0,32-1,30,30	/* _PAGE_USER -> PP msb */

	ori	r1, r1, 0xe05		/* clear out reserved bits */

	andc	r1, r0, r1		/* PP = user? 2 : 0 */

BEGIN_FTR_SECTION
@@ -590,8 +589,7 @@ DataLoadTLBMiss: 
	 * we would need to update the pte atomically with lwarx/stwcx.

	 */

	/* Convert linux-style PTE to low word of PPC-style PTE */

	rlwinm	r1,r0,32-10,31,31	/* _PAGE_RW -> PP lsb */

	rlwimi	r0,r0,32-1,30,30	/* _PAGE_USER -> PP msb */

	rlwinm	r1, r0, 0, 31, 31	/* _PAGE_RW -> PP lsb */

	rlwimi	r0,r0,32-1,31,31	/* _PAGE_USER -> PP lsb */

	ori	r1,r1,0xe04		/* clear out reserved bits */

	andc	r1,r0,r1		/* PP = user? rw? 2: 3: 0 */
@@ -670,7 +668,6 @@ DataStoreTLBMiss: 
	 * we would need to update the pte atomically with lwarx/stwcx.

	 */

	/* Convert linux-style PTE to low word of PPC-style PTE */

	rlwimi	r0,r0,32-1,30,30	/* _PAGE_USER -> PP msb */

	li	r1,0xe05		/* clear out reserved bits & PP lsb */

	andc	r1,r0,r1		/* PP = user? 2: 0 */

BEGIN_FTR_SECTION

arch/powerpc/mm/hash_low_32.S

+2 −4
Original line number Diff line number Diff line
@@ -310,11 +310,9 @@ Hash_msk = (((1 << Hash_bits) - 1) * 64) 


_GLOBAL(create_hpte)

	/* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */

	rlwinm	r8,r5,32-10,31,31	/* _PAGE_RW -> PP lsb */

	rlwinm	r0,r5,32-7,31,31	/* _PAGE_DIRTY -> PP lsb */

	and	r8,r8,r0		/* writable if _RW & _DIRTY */

	rlwimi	r5,r5,32-1,30,30	/* _PAGE_USER -> PP msb */

	rlwimi	r5,r5,32-2,31,31	/* _PAGE_USER -> PP lsb */

	and	r8, r5, r0		/* writable if _RW & _DIRTY */

	rlwimi	r5, r5, 32 - 1, 31, 31	/* _PAGE_USER -> PP lsb */

	ori	r8,r8,0xe04		/* clear out reserved bits */

	andc	r8,r5,r8		/* PP = user? (rw&dirty? 2: 3): 0 */

BEGIN_FTR_SECTION

CRA Git | Maintained and supported by SUSTech CRA and CCSE