Commit 78c2aac2 authored by Wesley Cheng's avatar Wesley Cheng Committed by Vinod Koul
Browse files

phy: qcom-qmp: Rename UFS PCS QMP v4 registers 



The UFS QMP v4 PHY has a largely different register set versus USB and
PCIe.  Rename the register offsets to denote that the value is specific for
the UFS PCS register.

Signed-off-by: default avatarWesley Cheng <wcheng@codeaurora.org>
Link: https://lore.kernel.org/r/1588636467-23409-6-git-send-email-wcheng@codeaurora.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent e4d8b05a

drivers/phy/qualcomm/phy-qcom-qmp.c

+10 −10
Original line number Diff line number Diff line
@@ -191,9 +191,9 @@ static const unsigned int sdm845_ufsphy_regs_layout[] = { 
};



static const unsigned int sm8150_ufsphy_regs_layout[] = {

	[QPHY_START_CTRL]		= QPHY_V4_PHY_START,

	[QPHY_PCS_READY_STATUS]		= QPHY_V4_PCS_READY_STATUS,

	[QPHY_SW_RESET]			= QPHY_V4_SW_RESET,

	[QPHY_START_CTRL]		= QPHY_V4_PCS_UFS_PHY_START,

	[QPHY_PCS_READY_STATUS]		= QPHY_V4_PCS_UFS_READY_STATUS,

	[QPHY_SW_RESET]			= QPHY_V4_PCS_UFS_SW_RESET,

};



static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
@@ -1280,13 +1280,13 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { 
};



static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_V4_RX_SIGDET_CTRL2, 0x6d),

	QMP_PHY_INIT_CFG(QPHY_V4_TX_LARGE_AMP_DRV_LVL, 0x0a),

	QMP_PHY_INIT_CFG(QPHY_V4_TX_SMALL_AMP_DRV_LVL, 0x02),

	QMP_PHY_INIT_CFG(QPHY_V4_TX_MID_TERM_CTRL1, 0x43),

	QMP_PHY_INIT_CFG(QPHY_V4_DEBUG_BUS_CLKSEL, 0x1f),

	QMP_PHY_INIT_CFG(QPHY_V4_RX_MIN_HIBERN8_TIME, 0xff),

	QMP_PHY_INIT_CFG(QPHY_V4_MULTI_LANE_CTRL1, 0x02),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),

};



static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {

drivers/phy/qualcomm/phy-qcom-qmp.h

+20 −20
Original line number Diff line number Diff line
@@ -425,26 +425,26 @@ 
#define QSERDES_V4_RX_VTH_CODE				0x1c4



/* Only for QMP V4 PHY - UFS PCS registers */

#define QPHY_V4_PHY_START				0x000

#define QPHY_V4_POWER_DOWN_CONTROL			0x004

#define QPHY_V4_SW_RESET				0x008

#define QPHY_V4_TIMER_20US_CORECLK_STEPS_MSB		0x00c

#define QPHY_V4_TIMER_20US_CORECLK_STEPS_LSB		0x010

#define QPHY_V4_PLL_CNTL				0x02c

#define QPHY_V4_TX_LARGE_AMP_DRV_LVL			0x030

#define QPHY_V4_TX_SMALL_AMP_DRV_LVL			0x038

#define QPHY_V4_BIST_FIXED_PAT_CTRL			0x060

#define QPHY_V4_TX_HSGEAR_CAPABILITY			0x074

#define QPHY_V4_RX_HSGEAR_CAPABILITY			0x0b4

#define QPHY_V4_DEBUG_BUS_CLKSEL			0x124

#define QPHY_V4_LINECFG_DISABLE				0x148

#define QPHY_V4_RX_MIN_HIBERN8_TIME			0x150

#define QPHY_V4_RX_SIGDET_CTRL2				0x158

#define QPHY_V4_TX_PWM_GEAR_BAND			0x160

#define QPHY_V4_TX_HS_GEAR_BAND				0x168

#define QPHY_V4_PCS_READY_STATUS			0x180

#define QPHY_V4_TX_MID_TERM_CTRL1			0x1d8

#define QPHY_V4_MULTI_LANE_CTRL1			0x1e0

#define QPHY_V4_PCS_UFS_PHY_START				0x000

#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL			0x004

#define QPHY_V4_PCS_UFS_SW_RESET				0x008

#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB		0x00c

#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB		0x010

#define QPHY_V4_PCS_UFS_PLL_CNTL				0x02c

#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL			0x030

#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL			0x038

#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL			0x060

#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY			0x074

#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY			0x0b4

#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL			0x124

#define QPHY_V4_PCS_UFS_LINECFG_DISABLE				0x148

#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME			0x150

#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2				0x158

#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND			0x160

#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND				0x168

#define QPHY_V4_PCS_UFS_READY_STATUS			0x180

#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1			0x1d8

#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1			0x1e0



/* PCIE GEN3 COM registers */

#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER			0x14

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