Unverified Commit 76d4467a authored by Qiu Wenbo's avatar Qiu Wenbo Committed by Palmer Dabbelt
Browse files

riscv: Setup exception vector for nommu platform 



Exception vector is missing on nommu platform and that is an issue.
This patch is tested in Sipeed Maix Bit Dev Board.

Fixes: 79b1feba ("RISC-V: Setup exception vector early")
Suggested-by: default avatarAnup Patel <anup@brainfault.org>
Suggested-by: default avatarAtish Patra <atishp@atishpatra.org>
Signed-off-by: default avatarQiu Wenbo <qiuwenbo@phytium.com.cn>
Reviewed-by: default avatarAtish Patra <atish.patra@wdc.com>
Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent dbf83817

arch/riscv/kernel/head.S

+17 −8
Original line number Diff line number Diff line
@@ -77,16 +77,10 @@ relocate: 
	csrw CSR_SATP, a0

.align 2

1:

	/* Set trap vector to exception handler */

	la a0, handle_exception

	/* Set trap vector to spin forever to help debug */

	la a0, .Lsecondary_park

	csrw CSR_TVEC, a0



	/*

	 * Set sup0 scratch register to 0, indicating to exception vector that

	 * we are presently executing in kernel.

	 */

	csrw CSR_SCRATCH, zero



	/* Reload the global pointer */

.option push

.option norelax
@@ -144,9 +138,23 @@ secondary_start_common: 
	la a0, swapper_pg_dir

	call relocate

#endif

	call setup_trap_vector

	tail smp_callin

#endif /* CONFIG_SMP */



.align 2

setup_trap_vector:

	/* Set trap vector to exception handler */

	la a0, handle_exception

	csrw CSR_TVEC, a0



	/*

	 * Set sup0 scratch register to 0, indicating to exception vector that

	 * we are presently executing in kernel.

	 */

	csrw CSR_SCRATCH, zero

	ret



.Lsecondary_park:

	/* We lack SMP support or have too many harts, so park this hart */

	wfi
@@ -240,6 +248,7 @@ clear_bss_done: 
	call relocate

#endif /* CONFIG_MMU */



	call setup_trap_vector

	/* Restore C environment */

	la tp, init_task

	sw zero, TASK_TI_CPU(tp)

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