Unverified Commit 79b1feba authored by Atish Patra's avatar Atish Patra Committed by Palmer Dabbelt
Browse files

RISC-V: Setup exception vector early 



The trap vector is set only in trap_init which may be too late in some
cases. Early ioremap/efi spits many warning messages which may be useful.

Setup the trap vector early so that any warning/bug can be handled before
generic code invokes trap_init.

Signed-off-by: default avatarAtish Patra <atish.patra@wdc.com>
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent 925ac7b6

arch/riscv/kernel/head.S

+8 −2
Original line number Diff line number Diff line
@@ -77,10 +77,16 @@ relocate: 
	csrw CSR_SATP, a0

.align 2

1:

	/* Set trap vector to spin forever to help debug */

	la a0, .Lsecondary_park

	/* Set trap vector to exception handler */

	la a0, handle_exception

	csrw CSR_TVEC, a0



	/*

	 * Set sup0 scratch register to 0, indicating to exception vector that

	 * we are presently executing in kernel.

	 */

	csrw CSR_SCRATCH, zero



	/* Reload the global pointer */

.option push

.option norelax

arch/riscv/kernel/smpboot.c

+1 −1
Original line number Diff line number Diff line
@@ -154,10 +154,10 @@ asmlinkage __visible void smp_callin(void) 
	mmgrab(mm);

	current->active_mm = mm;



	trap_init();

	notify_cpu_starting(curr_cpuid);

	update_siblings_masks(curr_cpuid);

	set_cpu_online(curr_cpuid, 1);



	/*

	 * Remote TLB flushes are ignored while the CPU is offline, so emit

	 * a local TLB flush right now just in case.

arch/riscv/kernel/traps.c

+1 −7
Original line number Diff line number Diff line
@@ -174,13 +174,7 @@ int is_valid_bugaddr(unsigned long pc) 
}

#endif /* CONFIG_GENERIC_BUG */



/* stvec & scratch is already set from head.S */

void trap_init(void)

{

	/*

	 * Set sup0 scratch register to 0, indicating to exception vector

	 * that we are presently executing in the kernel

	 */

	csr_write(CSR_SCRATCH, 0);

	/* Set the exception vector address */

	csr_write(CSR_TVEC, &handle_exception);

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE