clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxes (765b7d4c) · Commits · 戴 / test

Zynq's Ethernet clocks are created by the following hierarchy: mux0 ---> div0 ---> div1 ---> mux1 ---> gate Rate change requests on the gate have to propagate all the way up to div0 to properly leverage all dividers. Mux1 was missing the CLK_SET_RATE_PARENT flag, which is required to achieve this. This does not fix a specific regression but the clock driver was merged for 3.11-rc1, so best to fix the known bugs before the release. Signed-off-by:

Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by:

Michal Simek <michal.simek@xilinx.com> Signed-off-by:

Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: added to changelog]

drivers/clk/zynq/clkc.c

+6 −4

Original line number	Diff line number	Diff line
		@@ -365,8 +365,9 @@ static void __init zynq_clk_setup(struct device_node *np)
		CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
		CLK_DIVIDER_ONE_BASED \| CLK_DIVIDER_ALLOW_ZERO,
		&gem0clk_lock);
		clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 0,
		SLCR_GEM0_CLK_CTRL, 6, 1, 0, &gem0clk_lock);
		clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
		CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 6, 1, 0,
		&gem0clk_lock);
		clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
		"gem0_emio_mux", CLK_SET_RATE_PARENT,
		SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
		@@ -387,8 +388,9 @@ static void __init zynq_clk_setup(struct device_node *np)
		CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
		CLK_DIVIDER_ONE_BASED \| CLK_DIVIDER_ALLOW_ZERO,
		&gem1clk_lock);
		clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 0,
		SLCR_GEM1_CLK_CTRL, 6, 1, 0, &gem1clk_lock);
		clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
		CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 6, 1, 0,
		&gem1clk_lock);
		clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
		"gem1_emio_mux", CLK_SET_RATE_PARENT,
		SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);

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