clk/zynq/clkc: Add dedicated spinlock for the SWDT (252957cc) · Commits · 戴 / test

The clk_mux for the system watchdog timer reused the register lock dedicated to the Ethernet module - for no apparent reason. Add a lock dedicated to the SWDT's clock register to remove this wrong dependency. This does not fix a specific regression but the clock driver was merged for 3.11-rc1, so best to fix the known bugs before the release. Signed-off-by:

Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by:

Michal Simek <michal.simek@xilinx.com> Signed-off-by:

Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: added to changelog]

drivers/clk/zynq/clkc.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -71,6 +71,7 @@ static DEFINE_SPINLOCK(armpll_lock);
		static DEFINE_SPINLOCK(ddrpll_lock);
		static DEFINE_SPINLOCK(iopll_lock);
		static DEFINE_SPINLOCK(armclk_lock);
		static DEFINE_SPINLOCK(swdtclk_lock);
		static DEFINE_SPINLOCK(ddrclk_lock);
		static DEFINE_SPINLOCK(dciclk_lock);
		static DEFINE_SPINLOCK(gem0clk_lock);
		@@ -293,7 +294,7 @@ static void __init zynq_clk_setup(struct device_node *np)
		}
		clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
		swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT,
		SLCR_SWDT_CLK_SEL, 0, 1, 0, &gem0clk_lock);
		SLCR_SWDT_CLK_SEL, 0, 1, 0, &swdtclk_lock);

		/* DDR clocks */
		clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,

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