Commit 75e675f8 authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

Merge tag 'gvt-next-2020-03-10' of https://github.com/intel/gvt-linux into drm-intel-next-queued 



gvt-next-2020-03-10

- Fix CFL dmabuf display after vfio edid enabling (Tina)
- Clean up scan non-priv batch debugfs entry (Chris)
- Use intel engines initialized in gvt, cleanup previous ring id (Chris)
- Use intel_gt instead (Chris)

Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200310081928.GG28483@zhen-hp.sh.intel.com
parents 765e7cd9 a61ac1e7

drivers/gpu/drm/i915/gvt/aperture_gm.c

+44 −40
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ 
static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)

{

	struct intel_gvt *gvt = vgpu->gvt;

	struct drm_i915_private *dev_priv = gvt->dev_priv;

	struct intel_gt *gt = gvt->gt;

	unsigned int flags;

	u64 start, end, size;

	struct drm_mm_node *node;
@@ -61,14 +61,14 @@ static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm) 
		flags = PIN_MAPPABLE;

	}



	mutex_lock(&dev_priv->ggtt.vm.mutex);

	mmio_hw_access_pre(dev_priv);

	ret = i915_gem_gtt_insert(&dev_priv->ggtt.vm, node,

	mutex_lock(&gt->ggtt->vm.mutex);

	mmio_hw_access_pre(gt);

	ret = i915_gem_gtt_insert(&gt->ggtt->vm, node,

				  size, I915_GTT_PAGE_SIZE,

				  I915_COLOR_UNEVICTABLE,

				  start, end, flags);

	mmio_hw_access_post(dev_priv);

	mutex_unlock(&dev_priv->ggtt.vm.mutex);

	mmio_hw_access_post(gt);

	mutex_unlock(&gt->ggtt->vm.mutex);

	if (ret)

		gvt_err("fail to alloc %s gm space from host\n",

			high_gm ? "high" : "low");
@@ -79,7 +79,7 @@ static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm) 
static int alloc_vgpu_gm(struct intel_vgpu *vgpu)

{

	struct intel_gvt *gvt = vgpu->gvt;

	struct drm_i915_private *dev_priv = gvt->dev_priv;

	struct intel_gt *gt = gvt->gt;

	int ret;



	ret = alloc_gm(vgpu, false);
@@ -98,20 +98,21 @@ static int alloc_vgpu_gm(struct intel_vgpu *vgpu) 


	return 0;

out_free_aperture:

	mutex_lock(&dev_priv->ggtt.vm.mutex);

	mutex_lock(&gt->ggtt->vm.mutex);

	drm_mm_remove_node(&vgpu->gm.low_gm_node);

	mutex_unlock(&dev_priv->ggtt.vm.mutex);

	mutex_unlock(&gt->ggtt->vm.mutex);

	return ret;

}



static void free_vgpu_gm(struct intel_vgpu *vgpu)

{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	struct intel_gvt *gvt = vgpu->gvt;

	struct intel_gt *gt = gvt->gt;



	mutex_lock(&dev_priv->ggtt.vm.mutex);

	mutex_lock(&gt->ggtt->vm.mutex);

	drm_mm_remove_node(&vgpu->gm.low_gm_node);

	drm_mm_remove_node(&vgpu->gm.high_gm_node);

	mutex_unlock(&dev_priv->ggtt.vm.mutex);

	mutex_unlock(&gt->ggtt->vm.mutex);

}



/**
@@ -128,28 +129,29 @@ void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 
		u32 fence, u64 value)

{

	struct intel_gvt *gvt = vgpu->gvt;

	struct drm_i915_private *dev_priv = gvt->dev_priv;

	struct drm_i915_private *i915 = gvt->gt->i915;

	struct intel_uncore *uncore = gvt->gt->uncore;

	struct i915_fence_reg *reg;

	i915_reg_t fence_reg_lo, fence_reg_hi;



	assert_rpm_wakelock_held(&dev_priv->runtime_pm);

	assert_rpm_wakelock_held(uncore->rpm);



	if (drm_WARN_ON(&dev_priv->drm, fence >= vgpu_fence_sz(vgpu)))

	if (drm_WARN_ON(&i915->drm, fence >= vgpu_fence_sz(vgpu)))

		return;



	reg = vgpu->fence.regs[fence];

	if (drm_WARN_ON(&dev_priv->drm, !reg))

	if (drm_WARN_ON(&i915->drm, !reg))

		return;



	fence_reg_lo = FENCE_REG_GEN6_LO(reg->id);

	fence_reg_hi = FENCE_REG_GEN6_HI(reg->id);



	I915_WRITE(fence_reg_lo, 0);

	POSTING_READ(fence_reg_lo);

	intel_uncore_write(uncore, fence_reg_lo, 0);

	intel_uncore_posting_read(uncore, fence_reg_lo);



	I915_WRITE(fence_reg_hi, upper_32_bits(value));

	I915_WRITE(fence_reg_lo, lower_32_bits(value));

	POSTING_READ(fence_reg_lo);

	intel_uncore_write(uncore, fence_reg_hi, upper_32_bits(value));

	intel_uncore_write(uncore, fence_reg_lo, lower_32_bits(value));

	intel_uncore_posting_read(uncore, fence_reg_lo);

}



static void _clear_vgpu_fence(struct intel_vgpu *vgpu)
@@ -163,42 +165,43 @@ static void _clear_vgpu_fence(struct intel_vgpu *vgpu) 
static void free_vgpu_fence(struct intel_vgpu *vgpu)

{

	struct intel_gvt *gvt = vgpu->gvt;

	struct drm_i915_private *dev_priv = gvt->dev_priv;

	struct intel_uncore *uncore = gvt->gt->uncore;

	struct i915_fence_reg *reg;

	intel_wakeref_t wakeref;

	u32 i;



	if (drm_WARN_ON(&dev_priv->drm, !vgpu_fence_sz(vgpu)))

	if (drm_WARN_ON(&gvt->gt->i915->drm, !vgpu_fence_sz(vgpu)))

		return;



	intel_runtime_pm_get(&dev_priv->runtime_pm);

	wakeref = intel_runtime_pm_get(uncore->rpm);



	mutex_lock(&dev_priv->ggtt.vm.mutex);

	mutex_lock(&gvt->gt->ggtt->vm.mutex);

	_clear_vgpu_fence(vgpu);

	for (i = 0; i < vgpu_fence_sz(vgpu); i++) {

		reg = vgpu->fence.regs[i];

		i915_unreserve_fence(reg);

		vgpu->fence.regs[i] = NULL;

	}

	mutex_unlock(&dev_priv->ggtt.vm.mutex);

	mutex_unlock(&gvt->gt->ggtt->vm.mutex);



	intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm);

	intel_runtime_pm_put(uncore->rpm, wakeref);

}



static int alloc_vgpu_fence(struct intel_vgpu *vgpu)

{

	struct intel_gvt *gvt = vgpu->gvt;

	struct drm_i915_private *dev_priv = gvt->dev_priv;

	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;

	struct intel_uncore *uncore = gvt->gt->uncore;

	struct i915_fence_reg *reg;

	intel_wakeref_t wakeref;

	int i;



	intel_runtime_pm_get(rpm);

	wakeref = intel_runtime_pm_get(uncore->rpm);



	/* Request fences from host */

	mutex_lock(&dev_priv->ggtt.vm.mutex);

	mutex_lock(&gvt->gt->ggtt->vm.mutex);



	for (i = 0; i < vgpu_fence_sz(vgpu); i++) {

		reg = i915_reserve_fence(&dev_priv->ggtt);

		reg = i915_reserve_fence(gvt->gt->ggtt);

		if (IS_ERR(reg))

			goto out_free_fence;
@@ -207,9 +210,10 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu) 


	_clear_vgpu_fence(vgpu);



	mutex_unlock(&dev_priv->ggtt.vm.mutex);

	intel_runtime_pm_put_unchecked(rpm);

	mutex_unlock(&gvt->gt->ggtt->vm.mutex);

	intel_runtime_pm_put(uncore->rpm, wakeref);

	return 0;



out_free_fence:

	gvt_vgpu_err("Failed to alloc fences\n");

	/* Return fences to host, if fail */
@@ -220,8 +224,8 @@ out_free_fence: 
		i915_unreserve_fence(reg);

		vgpu->fence.regs[i] = NULL;

	}

	mutex_unlock(&dev_priv->ggtt.vm.mutex);

	intel_runtime_pm_put_unchecked(rpm);

	mutex_unlock(&gvt->gt->ggtt->vm.mutex);

	intel_runtime_pm_put_unchecked(uncore->rpm);

	return -ENOSPC;

}
@@ -315,11 +319,11 @@ void intel_vgpu_free_resource(struct intel_vgpu *vgpu) 
 */

void intel_vgpu_reset_resource(struct intel_vgpu *vgpu)

{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	struct intel_gvt *gvt = vgpu->gvt;

	intel_wakeref_t wakeref;



	intel_runtime_pm_get(&dev_priv->runtime_pm);

	with_intel_runtime_pm(gvt->gt->uncore->rpm, wakeref)

		_clear_vgpu_fence(vgpu);

	intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm);

}



/**

drivers/gpu/drm/i915/gvt/cfg_space.c

+4 −4
Original line number Diff line number Diff line
@@ -106,7 +106,7 @@ static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off, 
int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,

	void *p_data, unsigned int bytes)

{

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;

	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;



	if (drm_WARN_ON(&i915->drm, bytes > 4))

		return -EINVAL;
@@ -300,7 +300,7 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, 
int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,

	void *p_data, unsigned int bytes)

{

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;

	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;

	int ret;



	if (drm_WARN_ON(&i915->drm, bytes > 4))
@@ -396,9 +396,9 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 
	memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);



	vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size =

				pci_resource_len(gvt->dev_priv->drm.pdev, 0);

		pci_resource_len(gvt->gt->i915->drm.pdev, 0);

	vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size =

				pci_resource_len(gvt->dev_priv->drm.pdev, 2);

		pci_resource_len(gvt->gt->i915->drm.pdev, 2);



	memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4);

}

drivers/gpu/drm/i915/gvt/cmd_parser.c

+92 −112
Original line number Diff line number Diff line
@@ -462,7 +462,7 @@ enum { 


struct parser_exec_state {

	struct intel_vgpu *vgpu;

	int ring_id;

	const struct intel_engine_cs *engine;



	int buf_type;
@@ -635,39 +635,42 @@ static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = { 
	},

};



static inline u32 get_opcode(u32 cmd, int ring_id)

static inline u32 get_opcode(u32 cmd, const struct intel_engine_cs *engine)

{

	const struct decode_info *d_info;



	d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];

	d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];

	if (d_info == NULL)

		return INVALID_OP;



	return cmd >> (32 - d_info->op_len);

}



static inline const struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,

		unsigned int opcode, int ring_id)

static inline const struct cmd_info *

find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode,

	       const struct intel_engine_cs *engine)

{

	struct cmd_entry *e;



	hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {

		if (opcode == e->info->opcode && e->info->rings & BIT(ring_id))

		if (opcode == e->info->opcode &&

		    e->info->rings & engine->mask)

			return e->info;

	}

	return NULL;

}



static inline const struct cmd_info *get_cmd_info(struct intel_gvt *gvt,

		u32 cmd, int ring_id)

static inline const struct cmd_info *

get_cmd_info(struct intel_gvt *gvt, u32 cmd,

	     const struct intel_engine_cs *engine)

{

	u32 opcode;



	opcode = get_opcode(cmd, ring_id);

	opcode = get_opcode(cmd, engine);

	if (opcode == INVALID_OP)

		return NULL;



	return find_cmd_entry(gvt, opcode, ring_id);

	return find_cmd_entry(gvt, opcode, engine);

}



static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
@@ -675,12 +678,12 @@ static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low) 
	return (cmd >> low) & ((1U << (hi - low + 1)) - 1);

}



static inline void print_opcode(u32 cmd, int ring_id)

static inline void print_opcode(u32 cmd, const struct intel_engine_cs *engine)

{

	const struct decode_info *d_info;

	int i;



	d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];

	d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];

	if (d_info == NULL)

		return;
@@ -709,9 +712,10 @@ static void parser_exec_state_dump(struct parser_exec_state *s) 
	int cnt = 0;

	int i;



	gvt_dbg_cmd("  vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"

			" ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,

			s->ring_id, s->ring_start, s->ring_start + s->ring_size,

	gvt_dbg_cmd("  vgpu%d RING%s: ring_start(%08lx) ring_end(%08lx)"

		    " ring_head(%08lx) ring_tail(%08lx)\n",

		    s->vgpu->id, s->engine->name,

		    s->ring_start, s->ring_start + s->ring_size,

		    s->ring_head, s->ring_tail);



	gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
@@ -729,7 +733,7 @@ static void parser_exec_state_dump(struct parser_exec_state *s) 
			s->ip_va, cmd_val(s, 0), cmd_val(s, 1),

			cmd_val(s, 2), cmd_val(s, 3));



	print_opcode(cmd_val(s, 0), s->ring_id);

	print_opcode(cmd_val(s, 0), s->engine);



	s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
@@ -840,7 +844,6 @@ static int force_nonpriv_reg_handler(struct parser_exec_state *s, 
	unsigned int data;

	u32 ring_base;

	u32 nopid;

	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;



	if (!strcmp(cmd, "lri"))

		data = cmd_val(s, index + 1);
@@ -850,7 +853,7 @@ static int force_nonpriv_reg_handler(struct parser_exec_state *s, 
		return -EINVAL;

	}



	ring_base = dev_priv->engine[s->ring_id]->mmio_base;

	ring_base = s->engine->mmio_base;

	nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));



	if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
@@ -926,7 +929,7 @@ static int cmd_reg_handler(struct parser_exec_state *s, 
	 * update reg values in it into vregs, so LRIs in workload with

	 * inhibit context will restore with correct values

	 */

	if (IS_GEN(gvt->dev_priv, 9) &&

	if (IS_GEN(s->engine->i915, 9) &&

	    intel_gvt_mmio_is_in_ctx(gvt, offset) &&

	    !strncmp(cmd, "lri", 3)) {

		intel_gvt_hypervisor_read_gpa(s->vgpu,
@@ -964,7 +967,6 @@ static int cmd_handler_lri(struct parser_exec_state *s) 
{

	int i, ret = 0;

	int cmd_len = cmd_length(s);

	struct intel_gvt *gvt = s->vgpu->gvt;

	u32 valid_len = CMD_LEN(1);



	/*
@@ -979,8 +981,8 @@ static int cmd_handler_lri(struct parser_exec_state *s) 
	}



	for (i = 1; i < cmd_len; i += 2) {

		if (IS_BROADWELL(gvt->dev_priv) && s->ring_id != RCS0) {

			if (s->ring_id == BCS0 &&

		if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) {

			if (s->engine->id == BCS0 &&

			    cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))

				ret |= 0;

			else
@@ -1001,7 +1003,7 @@ static int cmd_handler_lrr(struct parser_exec_state *s) 
	int cmd_len = cmd_length(s);



	for (i = 1; i < cmd_len; i += 2) {

		if (IS_BROADWELL(s->vgpu->gvt->dev_priv))

		if (IS_BROADWELL(s->engine->i915))

			ret |= ((cmd_reg_inhibit(s, i) ||

				 (cmd_reg_inhibit(s, i + 1)))) ?

				-EBADRQC : 0;
@@ -1029,7 +1031,7 @@ static int cmd_handler_lrm(struct parser_exec_state *s) 
	int cmd_len = cmd_length(s);



	for (i = 1; i < cmd_len;) {

		if (IS_BROADWELL(gvt->dev_priv))

		if (IS_BROADWELL(s->engine->i915))

			ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;

		if (ret)

			break;
@@ -1141,7 +1143,7 @@ static int cmd_handler_pipe_control(struct parser_exec_state *s) 
				if (ret)

					return ret;

				if (index_mode) {

					hws_pga = s->vgpu->hws_pga[s->ring_id];

					hws_pga = s->vgpu->hws_pga[s->engine->id];

					gma = hws_pga + gma;

					patch_value(s, cmd_ptr(s, 2), gma);

					val = cmd_val(s, 1) & (~(1 << 21));
@@ -1155,14 +1157,14 @@ static int cmd_handler_pipe_control(struct parser_exec_state *s) 
		return ret;



	if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)

		set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,

		set_bit(cmd_interrupt_events[s->engine->id].pipe_control_notify,

			s->workload->pending_events);

	return 0;

}



static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)

{

	set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,

	set_bit(cmd_interrupt_events[s->engine->id].mi_user_interrupt,

		s->workload->pending_events);

	patch_value(s, cmd_ptr(s, 0), MI_NOOP);

	return 0;
@@ -1213,7 +1215,7 @@ struct plane_code_mapping { 
static int gen8_decode_mi_display_flip(struct parser_exec_state *s,

		struct mi_display_flip_command_info *info)

{

	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;

	struct drm_i915_private *dev_priv = s->engine->i915;

	struct plane_code_mapping gen8_plane_code[] = {

		[0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},

		[1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
@@ -1259,7 +1261,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s, 
static int skl_decode_mi_display_flip(struct parser_exec_state *s,

		struct mi_display_flip_command_info *info)

{

	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;

	struct drm_i915_private *dev_priv = s->engine->i915;

	struct intel_vgpu *vgpu = s->vgpu;

	u32 dword0 = cmd_val(s, 0);

	u32 dword1 = cmd_val(s, 1);
@@ -1318,13 +1320,12 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s, 
static int gen8_check_mi_display_flip(struct parser_exec_state *s,

		struct mi_display_flip_command_info *info)

{

	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;

	u32 stride, tile;



	if (!info->async_flip)

		return 0;



	if (INTEL_GEN(dev_priv) >= 9) {

	if (INTEL_GEN(s->engine->i915) >= 9) {

		stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);

		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &

				GENMASK(12, 10)) >> 10;
@@ -1347,7 +1348,7 @@ static int gen8_update_plane_mmio_from_mi_display_flip( 
		struct parser_exec_state *s,

		struct mi_display_flip_command_info *info)

{

	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;

	struct drm_i915_private *dev_priv = s->engine->i915;

	struct intel_vgpu *vgpu = s->vgpu;



	set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
@@ -1378,11 +1379,9 @@ static int gen8_update_plane_mmio_from_mi_display_flip( 
static int decode_mi_display_flip(struct parser_exec_state *s,

		struct mi_display_flip_command_info *info)

{

	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;



	if (IS_BROADWELL(dev_priv))

	if (IS_BROADWELL(s->engine->i915))

		return gen8_decode_mi_display_flip(s, info);

	if (INTEL_GEN(dev_priv) >= 9)

	if (INTEL_GEN(s->engine->i915) >= 9)

		return skl_decode_mi_display_flip(s, info);



	return -ENODEV;
@@ -1667,7 +1666,7 @@ static int cmd_handler_mi_flush_dw(struct parser_exec_state *s) 
		if (ret)

			return ret;

		if (index_mode) {

			hws_pga = s->vgpu->hws_pga[s->ring_id];

			hws_pga = s->vgpu->hws_pga[s->engine->id];

			gma = hws_pga + gma;

			patch_value(s, cmd_ptr(s, 1), gma);

			val = cmd_val(s, 0) & (~(1 << 21));
@@ -1676,7 +1675,7 @@ static int cmd_handler_mi_flush_dw(struct parser_exec_state *s) 
	}

	/* Check notify bit */

	if ((cmd_val(s, 0) & (1 << 8)))

		set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,

		set_bit(cmd_interrupt_events[s->engine->id].mi_flush_dw,

			s->workload->pending_events);

	return ret;

}
@@ -1725,12 +1724,18 @@ static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm, 
static int batch_buffer_needs_scan(struct parser_exec_state *s)

{

	/* Decide privilege based on address space */

	if (cmd_val(s, 0) & (1 << 8) &&

			!(s->vgpu->scan_nonprivbb & (1 << s->ring_id)))

	if (cmd_val(s, 0) & BIT(8) &&

	    !(s->vgpu->scan_nonprivbb & s->engine->mask))

		return 0;



	return 1;

}



static const char *repr_addr_type(unsigned int type)

{

	return type == PPGTT_BUFFER ? "ppgtt" : "ggtt";

}



static int find_bb_size(struct parser_exec_state *s,

			unsigned long *bb_size,

			unsigned long *bb_end_cmd_offset)
@@ -1753,24 +1758,24 @@ static int find_bb_size(struct parser_exec_state *s, 
		return -EFAULT;



	cmd = cmd_val(s, 0);

	info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);

	info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);

	if (info == NULL) {

		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",

				cmd, get_opcode(cmd, s->ring_id),

				(s->buf_addr_type == PPGTT_BUFFER) ?

				"ppgtt" : "ggtt", s->ring_id, s->workload);

		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",

			     cmd, get_opcode(cmd, s->engine),

			     repr_addr_type(s->buf_addr_type),

			     s->engine->name, s->workload);

		return -EBADRQC;

	}

	do {

		if (copy_gma_to_hva(s->vgpu, mm,

				    gma, gma + 4, &cmd) < 0)

			return -EFAULT;

		info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);

		info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);

		if (info == NULL) {

			gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",

				cmd, get_opcode(cmd, s->ring_id),

				(s->buf_addr_type == PPGTT_BUFFER) ?

				"ppgtt" : "ggtt", s->ring_id, s->workload);

			gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",

				     cmd, get_opcode(cmd, s->engine),

				     repr_addr_type(s->buf_addr_type),

				     s->engine->name, s->workload);

			return -EBADRQC;

		}
@@ -1799,12 +1804,12 @@ static int audit_bb_end(struct parser_exec_state *s, void *va) 
	u32 cmd = *(u32 *)va;

	const struct cmd_info *info;



	info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);

	info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);

	if (info == NULL) {

		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",

			cmd, get_opcode(cmd, s->ring_id),

			(s->buf_addr_type == PPGTT_BUFFER) ?

			"ppgtt" : "ggtt", s->ring_id, s->workload);

		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",

			     cmd, get_opcode(cmd, s->engine),

			     repr_addr_type(s->buf_addr_type),

			     s->engine->name, s->workload);

		return -EBADRQC;

	}
@@ -1857,7 +1862,7 @@ static int perform_bb_shadow(struct parser_exec_state *s) 
	if (bb->ppgtt)

		start_offset = gma & ~I915_GTT_PAGE_MASK;



	bb->obj = i915_gem_object_create_shmem(s->vgpu->gvt->dev_priv,

	bb->obj = i915_gem_object_create_shmem(s->engine->i915,

					       round_up(bb_size + start_offset,

							PAGE_SIZE));

	if (IS_ERR(bb->obj)) {
@@ -2666,19 +2671,19 @@ static int cmd_parser_exec(struct parser_exec_state *s) 
	if (cmd == MI_NOOP)

		info = &cmd_info[mi_noop_index];

	else

		info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);

		info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);



	if (info == NULL) {

		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",

				cmd, get_opcode(cmd, s->ring_id),

				(s->buf_addr_type == PPGTT_BUFFER) ?

				"ppgtt" : "ggtt", s->ring_id, s->workload);

		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",

			     cmd, get_opcode(cmd, s->engine),

			     repr_addr_type(s->buf_addr_type),

			     s->engine->name, s->workload);

		return -EBADRQC;

	}



	s->info = info;



	trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va,

	trace_gvt_command(vgpu->id, s->engine->id, s->ip_gma, s->ip_va,

			  cmd_length(s), s->buf_type, s->buf_addr_type,

			  s->workload, info->name);
@@ -2781,7 +2786,7 @@ static int scan_workload(struct intel_vgpu_workload *workload) 
	s.buf_type = RING_BUFFER_INSTRUCTION;

	s.buf_addr_type = GTT_BUFFER;

	s.vgpu = workload->vgpu;

	s.ring_id = workload->ring_id;

	s.engine = workload->engine;

	s.ring_start = workload->rb_start;

	s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);

	s.ring_head = gma_head;
@@ -2790,8 +2795,7 @@ static int scan_workload(struct intel_vgpu_workload *workload) 
	s.workload = workload;

	s.is_ctx_wa = false;



	if ((bypass_scan_mask & (1 << workload->ring_id)) ||

		gma_head == gma_tail)

	if (bypass_scan_mask & workload->engine->mask || gma_head == gma_tail)

		return 0;



	ret = ip_gma_set(&s, gma_head);
@@ -2830,7 +2834,7 @@ static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 
	s.buf_type = RING_BUFFER_INSTRUCTION;

	s.buf_addr_type = GTT_BUFFER;

	s.vgpu = workload->vgpu;

	s.ring_id = workload->ring_id;

	s.engine = workload->engine;

	s.ring_start = wa_ctx->indirect_ctx.guest_gma;

	s.ring_size = ring_size;

	s.ring_head = gma_head;
@@ -2855,7 +2859,6 @@ static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload) 
	struct intel_vgpu_submission *s = &vgpu->submission;

	unsigned long gma_head, gma_tail, gma_top, guest_rb_size;

	void *shadow_ring_buffer_va;

	int ring_id = workload->ring_id;

	int ret;



	guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
@@ -2868,21 +2871,21 @@ static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload) 
	gma_tail = workload->rb_start + workload->rb_tail;

	gma_top = workload->rb_start + guest_rb_size;



	if (workload->rb_len > s->ring_scan_buffer_size[ring_id]) {

	if (workload->rb_len > s->ring_scan_buffer_size[workload->engine->id]) {

		void *p;



		/* realloc the new ring buffer if needed */

		p = krealloc(s->ring_scan_buffer[ring_id], workload->rb_len,

				GFP_KERNEL);

		p = krealloc(s->ring_scan_buffer[workload->engine->id],

			     workload->rb_len, GFP_KERNEL);

		if (!p) {

			gvt_vgpu_err("fail to re-alloc ring scan buffer\n");

			return -ENOMEM;

		}

		s->ring_scan_buffer[ring_id] = p;

		s->ring_scan_buffer_size[ring_id] = workload->rb_len;

		s->ring_scan_buffer[workload->engine->id] = p;

		s->ring_scan_buffer_size[workload->engine->id] = workload->rb_len;

	}



	shadow_ring_buffer_va = s->ring_scan_buffer[ring_id];

	shadow_ring_buffer_va = s->ring_scan_buffer[workload->engine->id];



	/* get shadow ring buffer va */

	workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
@@ -2940,7 +2943,7 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) 
	int ret = 0;

	void *map;



	obj = i915_gem_object_create_shmem(workload->vgpu->gvt->dev_priv,

	obj = i915_gem_object_create_shmem(workload->engine->i915,

					   roundup(ctx_size + CACHELINE_BYTES,

						   PAGE_SIZE));

	if (IS_ERR(obj))
@@ -3029,30 +3032,14 @@ int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 
	return 0;

}



static const struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,

		unsigned int opcode, unsigned long rings)

{

	const struct cmd_info *info = NULL;

	unsigned int ring;



	for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {

		info = find_cmd_entry(gvt, opcode, ring);

		if (info)

			break;

	}

	return info;

}



static int init_cmd_table(struct intel_gvt *gvt)

{

	unsigned int gen_type = intel_gvt_get_device_type(gvt);

	int i;

	struct cmd_entry *e;

	const struct cmd_info *info;

	unsigned int gen_type;



	gen_type = intel_gvt_get_device_type(gvt);



	for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {

		struct cmd_entry *e;



		if (!(cmd_info[i].devices & gen_type))

			continue;
@@ -3061,14 +3048,6 @@ static int init_cmd_table(struct intel_gvt *gvt) 
			return -ENOMEM;



		e->info = &cmd_info[i];

		info = find_cmd_entry_any_ring(gvt,

				e->info->opcode, e->info->rings);

		if (info) {

			gvt_err("%s %s duplicated\n", e->info->name,

					info->name);

			kfree(e);

			return -EEXIST;

		}

		if (cmd_info[i].opcode == OP_MI_NOOP)

			mi_noop_index = i;
@@ -3078,6 +3057,7 @@ static int init_cmd_table(struct intel_gvt *gvt) 
			    e->info->name, e->info->opcode, e->info->flag,

			    e->info->devices, e->info->rings);

	}



	return 0;

}

drivers/gpu/drm/i915/gvt/debugfs.c

+5 −40
Original line number Diff line number Diff line
@@ -58,12 +58,11 @@ static int mmio_offset_compare(void *priv, 
static inline int mmio_diff_handler(struct intel_gvt *gvt,

				    u32 offset, void *data)

{

	struct drm_i915_private *i915 = gvt->dev_priv;

	struct mmio_diff_param *param = data;

	struct diff_mmio *node;

	u32 preg, vreg;



	preg = intel_uncore_read_notrace(&i915->uncore, _MMIO(offset));

	preg = intel_uncore_read_notrace(gvt->gt->uncore, _MMIO(offset));

	vreg = vgpu_vreg(param->vgpu, offset);



	if (preg != vreg) {
@@ -98,10 +97,10 @@ static int vgpu_mmio_diff_show(struct seq_file *s, void *unused) 
	mutex_lock(&gvt->lock);

	spin_lock_bh(&gvt->scheduler.mmio_context_lock);



	mmio_hw_access_pre(gvt->dev_priv);

	mmio_hw_access_pre(gvt->gt);

	/* Recognize all the diff mmios to list. */

	intel_gvt_for_each_tracked_mmio(gvt, mmio_diff_handler, &param);

	mmio_hw_access_post(gvt->dev_priv);

	mmio_hw_access_post(gvt->gt);



	spin_unlock_bh(&gvt->scheduler.mmio_context_lock);

	mutex_unlock(&gvt->lock);
@@ -128,6 +127,7 @@ static int 
vgpu_scan_nonprivbb_get(void *data, u64 *val)

{

	struct intel_vgpu *vgpu = (struct intel_vgpu *)data;



	*val = vgpu->scan_nonprivbb;

	return 0;

}
@@ -142,42 +142,7 @@ static int 
vgpu_scan_nonprivbb_set(void *data, u64 val)

{

	struct intel_vgpu *vgpu = (struct intel_vgpu *)data;

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	enum intel_engine_id id;

	char buf[128], *s;

	int len;



	val &= (1 << I915_NUM_ENGINES) - 1;



	if (vgpu->scan_nonprivbb == val)

		return 0;



	if (!val)

		goto done;



	len = sprintf(buf,

		"gvt: vgpu %d turns on non-privileged batch buffers scanning on Engines:",

		vgpu->id);



	s = buf + len;



	for (id = 0; id < I915_NUM_ENGINES; id++) {

		struct intel_engine_cs *engine;



		engine = dev_priv->engine[id];

		if (engine && (val & (1 << id))) {

			len = snprintf(s, 4, "%d, ", engine->id);

			s += len;

		} else

			val &=  ~(1 << id);

	}



	if (val)

		sprintf(s, "low performance expected.");



	pr_warn("%s\n", buf);



done:

	vgpu->scan_nonprivbb = val;

	return 0;

}
@@ -220,7 +185,7 @@ void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu) 
 */

void intel_gvt_debugfs_init(struct intel_gvt *gvt)

{

	struct drm_minor *minor = gvt->dev_priv->drm.primary;

	struct drm_minor *minor = gvt->gt->i915->drm.primary;



	gvt->debugfs_root = debugfs_create_dir("gvt", minor->debugfs_root);

drivers/gpu/drm/i915/gvt/display.c

+11 −10

File changed.

Preview size limit exceeded, changes collapsed.

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