Commit 75dee3b6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mailbox-v5.9' of git://git.linaro.org/landing-teams/working/fujitsu/integration 

Pull mailbox updates from Jassi Brar:
 "mediatek:
   - add support for mt6779 gce
   - shutdown cleanup and address shift support

  qcom:
   - add msm8994 apcs and sdm660 hmss compatibility

  imx:
   - mark PM funcs __maybe

  pcc:
   - put acpi table before bailout

  misc:
   - replace http with https links"

* tag 'mailbox-v5.9' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: mediatek: cmdq: clear task in channel before shutdown
  mailbox: cmdq: support mt6779 gce platform definition
  mailbox: cmdq: variablize address shift in platform
  dt-binding: gce: add gce header file for mt6779
  mailbox: qcom: Add msm8994 apcs compatible
  mailbox: qcom: Add sdm660 hmss compatible
  mailbox: imx: Mark PM functions as __maybe_unused
  mailbox: pcc: Put the PCCT table for error path
  mailbox: Replace HTTP links with HTTPS ones
parents ce615f5c 88499698

Documentation/devicetree/bindings/mailbox/mtk-gce.txt

+5 −3
Original line number Diff line number Diff line
@@ -9,7 +9,8 @@ CMDQ driver uses mailbox framework for communication. Please refer to 
mailbox.txt for generic information about mailbox device-tree bindings.



Required properties:

- compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce"

- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or

  "mediatek,mt6779-gce".

- reg: Address range of the GCE unit

- interrupts: The interrupt signal from the GCE block

- clock: Clocks according to the common clock binding
@@ -34,8 +35,9 @@ Optional properties for a client device: 
  start_offset: the start offset of register address that GCE can access.

  size: the total size of register address that GCE can access.



Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'

or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids.

Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h',

'dt-binding/gce/mt8183-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. Such as

sub-system ids, thread priority, event ids.



Example:

Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml

+2 −0
Original line number Diff line number Diff line
@@ -18,10 +18,12 @@ properties: 
    enum:

      - qcom,ipq8074-apcs-apps-global

      - qcom,msm8916-apcs-kpss-global

      - qcom,msm8994-apcs-kpss-global

      - qcom,msm8996-apcs-hmss-global

      - qcom,msm8998-apcs-hmss-global

      - qcom,qcs404-apcs-apps-global

      - qcom,sc7180-apss-shared

      - qcom,sdm660-apcs-hmss-global

      - qcom,sdm845-apss-shared

      - qcom,sm8150-apss-shared

drivers/mailbox/imx-mailbox.c

+4 −4
Original line number Diff line number Diff line
@@ -598,7 +598,7 @@ static const struct of_device_id imx_mu_dt_ids[] = { 
};

MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);



static int imx_mu_suspend_noirq(struct device *dev)

static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)

{

	struct imx_mu_priv *priv = dev_get_drvdata(dev);
@@ -608,7 +608,7 @@ static int imx_mu_suspend_noirq(struct device *dev) 
	return 0;

}



static int imx_mu_resume_noirq(struct device *dev)

static int __maybe_unused imx_mu_resume_noirq(struct device *dev)

{

	struct imx_mu_priv *priv = dev_get_drvdata(dev);
@@ -626,7 +626,7 @@ static int imx_mu_resume_noirq(struct device *dev) 
	return 0;

}



static int imx_mu_runtime_suspend(struct device *dev)

static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)

{

	struct imx_mu_priv *priv = dev_get_drvdata(dev);
@@ -635,7 +635,7 @@ static int imx_mu_runtime_suspend(struct device *dev) 
	return 0;

}



static int imx_mu_runtime_resume(struct device *dev)

static int __maybe_unused imx_mu_runtime_resume(struct device *dev)

{

	struct imx_mu_priv *priv = dev_get_drvdata(dev);

	int ret;

drivers/mailbox/mtk-cmdq-mailbox.c

+84 −13
Original line number Diff line number Diff line
@@ -75,8 +75,22 @@ struct cmdq { 
	struct cmdq_thread	*thread;

	struct clk		*clock;

	bool			suspended;

	u8			shift_pa;

};



struct gce_plat {

	u32 thread_nr;

	u8 shift;

};



u8 cmdq_get_shift_pa(struct mbox_chan *chan)

{

	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);



	return cmdq->shift_pa;

}

EXPORT_SYMBOL(cmdq_get_shift_pa);



static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)

{

	u32 status;
@@ -183,13 +197,15 @@ static void cmdq_task_handle_error(struct cmdq_task *task) 
{

	struct cmdq_thread *thread = task->thread;

	struct cmdq_task *next_task;

	struct cmdq *cmdq = task->cmdq;



	dev_err(task->cmdq->mbox.dev, "task 0x%p error\n", task);

	WARN_ON(cmdq_thread_suspend(task->cmdq, thread) < 0);

	dev_err(cmdq->mbox.dev, "task 0x%p error\n", task);

	WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);

	next_task = list_first_entry_or_null(&thread->task_busy_list,

			struct cmdq_task, list_entry);

	if (next_task)

		writel(next_task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);

		writel(next_task->pa_base >> cmdq->shift_pa,

		       thread->base + CMDQ_THR_CURR_ADDR);

	cmdq_thread_resume(thread);

}
@@ -219,7 +235,7 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq, 
	else

		return;



	curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);

	curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa;



	list_for_each_entry_safe(task, tmp, &thread->task_busy_list,

				 list_entry) {
@@ -333,29 +349,39 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data) 


	if (list_empty(&thread->task_busy_list)) {

		WARN_ON(clk_enable(cmdq->clock) < 0);

		/*

		 * The thread reset will clear thread related register to 0,

		 * including pc, end, priority, irq, suspend and enable. Thus

		 * set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable

		 * thread and make it running.

		 */

		WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);



		writel(task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);

		writel(task->pa_base + pkt->cmd_buf_size,

		writel(task->pa_base >> cmdq->shift_pa,

		       thread->base + CMDQ_THR_CURR_ADDR);

		writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,

		       thread->base + CMDQ_THR_END_ADDR);



		writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);

		writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);

		writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);

	} else {

		WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);

		curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);

		end_pa = readl(thread->base + CMDQ_THR_END_ADDR);

		curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<

			cmdq->shift_pa;

		end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<

			cmdq->shift_pa;

		/* check boundary */

		if (curr_pa == end_pa - CMDQ_INST_SIZE ||

		    curr_pa == end_pa) {

			/* set to this task directly */

			writel(task->pa_base,

			writel(task->pa_base >> cmdq->shift_pa,

			       thread->base + CMDQ_THR_CURR_ADDR);

		} else {

			cmdq_task_insert_into_thread(task);

			smp_mb(); /* modify jump before enable thread */

		}

		writel(task->pa_base + pkt->cmd_buf_size,

		writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,

		       thread->base + CMDQ_THR_END_ADDR);

		cmdq_thread_resume(thread);

	}
@@ -371,6 +397,38 @@ static int cmdq_mbox_startup(struct mbox_chan *chan) 


static void cmdq_mbox_shutdown(struct mbox_chan *chan)

{

	struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;

	struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);

	struct cmdq_task *task, *tmp;

	unsigned long flags;



	spin_lock_irqsave(&thread->chan->lock, flags);

	if (list_empty(&thread->task_busy_list))

		goto done;



	WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);



	/* make sure executed tasks have success callback */

	cmdq_thread_irq_handler(cmdq, thread);

	if (list_empty(&thread->task_busy_list))

		goto done;



	list_for_each_entry_safe(task, tmp, &thread->task_busy_list,

				 list_entry) {

		cmdq_task_exec_done(task, CMDQ_CB_ERROR);

		kfree(task);

	}



	cmdq_thread_disable(cmdq, thread);

	clk_disable(cmdq->clock);

done:

	/*

	 * The thread->task_busy_list empty means thread already disable. The

	 * cmdq_mbox_send_data() always reset thread which clear disable and

	 * suspend statue when first pkt send to channel, so there is no need

	 * to do any operation here, only unlock and leave.

	 */

	spin_unlock_irqrestore(&thread->chan->lock, flags);

}



static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout)
@@ -453,6 +511,7 @@ static int cmdq_probe(struct platform_device *pdev) 
	struct resource *res;

	struct cmdq *cmdq;

	int err, i;

	struct gce_plat *plat_data;



	cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);

	if (!cmdq)
@@ -471,7 +530,14 @@ static int cmdq_probe(struct platform_device *pdev) 
		return -EINVAL;

	}



	cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);

	plat_data = (struct gce_plat *)of_device_get_match_data(dev);

	if (!plat_data) {

		dev_err(dev, "failed to get match data\n");

		return -EINVAL;

	}



	cmdq->thread_nr = plat_data->thread_nr;

	cmdq->shift_pa = plat_data->shift;

	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);

	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,

			       "mtk_cmdq", cmdq);
@@ -534,9 +600,14 @@ static const struct dev_pm_ops cmdq_pm_ops = { 
	.resume = cmdq_resume,

};



static const struct gce_plat gce_plat_v2 = {.thread_nr = 16};

static const struct gce_plat gce_plat_v3 = {.thread_nr = 24};

static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3};



static const struct of_device_id cmdq_of_ids[] = {

	{.compatible = "mediatek,mt8173-gce", .data = (void *)16},

	{.compatible = "mediatek,mt8183-gce", .data = (void *)24},

	{.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},

	{.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},

	{.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},

	{}

};

drivers/mailbox/omap-mailbox.c

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
 * OMAP mailbox driver

 *

 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.

 * Copyright (C) 2013-2019 Texas Instruments Incorporated - http://www.ti.com

 * Copyright (C) 2013-2019 Texas Instruments Incorporated - https://www.ti.com

 *

 * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>

 *          Suman Anna <s-anna@ti.com>

CRA Git | Maintained and supported by SUSTech CRA and CCSE