Commit 6fc376f0 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'mediatek-drm-next-5.6' of https://github.com/ckhu-mediatek/linux.git-tags into drm-next 



Mediatek DRM Next for Linux 5.6

This fix non-smooth cursor problem, add cmdq support, add ctm property
support and some refinement.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: CK Hu <ck.hu@mediatek.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1578972526.14594.8.camel@mtksdaap41
parents fd7226fb d04a07a8

drivers/gpu/drm/mediatek/mtk_disp_color.c

+4 −3
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/of_device.h>

#include <linux/of_irq.h>

#include <linux/platform_device.h>

#include <linux/soc/mediatek/mtk-cmdq.h>



#include "mtk_drm_crtc.h"

#include "mtk_drm_ddp_comp.h"
@@ -45,12 +46,12 @@ static inline struct mtk_disp_color *comp_to_color(struct mtk_ddp_comp *comp) 


static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,

			     unsigned int h, unsigned int vrefresh,

			     unsigned int bpc)

			     unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

{

	struct mtk_disp_color *color = comp_to_color(comp);



	writel(w, comp->regs + DISP_COLOR_WIDTH(color));

	writel(h, comp->regs + DISP_COLOR_HEIGHT(color));

	mtk_ddp_write(cmdq_pkt, w, comp, DISP_COLOR_WIDTH(color));

	mtk_ddp_write(cmdq_pkt, h, comp, DISP_COLOR_HEIGHT(color));

}



static void mtk_color_start(struct mtk_ddp_comp *comp)

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

+40 −36
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <linux/of_device.h>

#include <linux/of_irq.h>

#include <linux/platform_device.h>

#include <linux/soc/mediatek/mtk-cmdq.h>



#include "mtk_drm_crtc.h"

#include "mtk_drm_ddp_comp.h"
@@ -124,14 +125,15 @@ static void mtk_ovl_stop(struct mtk_ddp_comp *comp) 


static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,

			   unsigned int h, unsigned int vrefresh,

			   unsigned int bpc)

			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

{

	if (w != 0 && h != 0)

		writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE);

	writel_relaxed(0x0, comp->regs + DISP_REG_OVL_ROI_BGCLR);

		mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, comp,

				      DISP_REG_OVL_ROI_SIZE);

	mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, DISP_REG_OVL_ROI_BGCLR);



	writel(0x1, comp->regs + DISP_REG_OVL_RST);

	writel(0x0, comp->regs + DISP_REG_OVL_RST);

	mtk_ddp_write(cmdq_pkt, 0x1, comp, DISP_REG_OVL_RST);

	mtk_ddp_write(cmdq_pkt, 0x0, comp, DISP_REG_OVL_RST);

}



static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)
@@ -175,16 +177,16 @@ static int mtk_ovl_layer_check(struct mtk_ddp_comp *comp, unsigned int idx, 
	return 0;

}



static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)

static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx,

			     struct cmdq_pkt *cmdq_pkt)

{

	unsigned int reg;

	unsigned int gmc_thrshd_l;

	unsigned int gmc_thrshd_h;

	unsigned int gmc_value;

	struct mtk_disp_ovl *ovl = comp_to_ovl(comp);



	writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));



	mtk_ddp_write(cmdq_pkt, 0x1, comp,

		      DISP_REG_OVL_RDMA_CTRL(idx));

	gmc_thrshd_l = GMC_THRESHOLD_LOW >>

		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);

	gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
@@ -194,22 +196,19 @@ static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx) 
	else

		gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |

			    gmc_thrshd_h << 16 | gmc_thrshd_h << 24;

	writel(gmc_value, comp->regs + DISP_REG_OVL_RDMA_GMC(idx));



	reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);

	reg = reg | BIT(idx);

	writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);

	mtk_ddp_write(cmdq_pkt, gmc_value,

		      comp, DISP_REG_OVL_RDMA_GMC(idx));

	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), comp,

			   DISP_REG_OVL_SRC_CON, BIT(idx));

}



static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx)

static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx,

			      struct cmdq_pkt *cmdq_pkt)

{

	unsigned int reg;



	reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);

	reg = reg & ~BIT(idx);

	writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);



	writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));

	mtk_ddp_write_mask(cmdq_pkt, 0, comp,

			   DISP_REG_OVL_SRC_CON, BIT(idx));

	mtk_ddp_write(cmdq_pkt, 0, comp,

		      DISP_REG_OVL_RDMA_CTRL(idx));

}



static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
@@ -249,7 +248,8 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) 
}



static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,

				 struct mtk_plane_state *state)

				 struct mtk_plane_state *state,

				 struct cmdq_pkt *cmdq_pkt)

{

	struct mtk_disp_ovl *ovl = comp_to_ovl(comp);

	struct mtk_plane_pending_state *pending = &state->pending;
@@ -260,11 +260,13 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, 
	unsigned int src_size = (pending->height << 16) | pending->width;

	unsigned int con;



	if (!pending->enable)

		mtk_ovl_layer_off(comp, idx);

	if (!pending->enable) {

		mtk_ovl_layer_off(comp, idx, cmdq_pkt);

		return;

	}



	con = ovl_fmt_convert(ovl, fmt);

	if (idx != 0)

	if (state->base.fb->format->has_alpha)

		con |= OVL_CON_AEN | OVL_CON_ALPHA;



	if (pending->rotation & DRM_MODE_REFLECT_Y) {
@@ -277,14 +279,18 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, 
		addr += pending->pitch - 1;

	}



	writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx));

	writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx));

	writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx));

	writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx));

	writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(ovl, idx));



	if (pending->enable)

		mtk_ovl_layer_on(comp, idx);

	mtk_ddp_write_relaxed(cmdq_pkt, con, comp,

			      DISP_REG_OVL_CON(idx));

	mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp,

			      DISP_REG_OVL_PITCH(idx));

	mtk_ddp_write_relaxed(cmdq_pkt, src_size, comp,

			      DISP_REG_OVL_SRC_SIZE(idx));

	mtk_ddp_write_relaxed(cmdq_pkt, offset, comp,

			      DISP_REG_OVL_OFFSET(idx));

	mtk_ddp_write_relaxed(cmdq_pkt, addr, comp,

			      DISP_REG_OVL_ADDR(ovl, idx));



	mtk_ovl_layer_on(comp, idx, cmdq_pkt);

}



static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp)
@@ -313,8 +319,6 @@ static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = { 
	.disable_vblank = mtk_ovl_disable_vblank,

	.supported_rotations = mtk_ovl_supported_rotations,

	.layer_nr = mtk_ovl_layer_nr,

	.layer_on = mtk_ovl_layer_on,

	.layer_off = mtk_ovl_layer_off,

	.layer_check = mtk_ovl_layer_check,

	.layer_config = mtk_ovl_layer_config,

	.bgclr_in_on = mtk_ovl_bgclr_in_on,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

+25 −18
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/of_device.h>

#include <linux/of_irq.h>

#include <linux/platform_device.h>

#include <linux/soc/mediatek/mtk-cmdq.h>



#include "mtk_drm_crtc.h"

#include "mtk_drm_ddp_comp.h"
@@ -125,14 +126,16 @@ static void mtk_rdma_stop(struct mtk_ddp_comp *comp) 


static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,

			    unsigned int height, unsigned int vrefresh,

			    unsigned int bpc)

			    unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

{

	unsigned int threshold;

	unsigned int reg;

	struct mtk_disp_rdma *rdma = comp_to_rdma(comp);



	rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);

	rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);

	mtk_ddp_write_mask(cmdq_pkt, width, comp,

			   DISP_REG_RDMA_SIZE_CON_0, 0xfff);

	mtk_ddp_write_mask(cmdq_pkt, height, comp,

			   DISP_REG_RDMA_SIZE_CON_1, 0xfffff);



	/*

	 * Enable FIFO underflow since DSI and DPI can't be blocked.
@@ -144,7 +147,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, 
	reg = RDMA_FIFO_UNDERFLOW_EN |

	      RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) |

	      RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);

	writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);

	mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON);

}



static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
@@ -190,7 +193,8 @@ static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp) 
}



static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,

				  struct mtk_plane_state *state)

				  struct mtk_plane_state *state,

				  struct cmdq_pkt *cmdq_pkt)

{

	struct mtk_disp_rdma *rdma = comp_to_rdma(comp);

	struct mtk_plane_pending_state *pending = &state->pending;
@@ -200,24 +204,27 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, 
	unsigned int con;



	con = rdma_fmt_convert(rdma, fmt);

	writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);

	mtk_ddp_write_relaxed(cmdq_pkt, con, comp, DISP_RDMA_MEM_CON);



	if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {

		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,

				 RDMA_MATRIX_ENABLE, RDMA_MATRIX_ENABLE);

		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,

				 RDMA_MATRIX_INT_MTX_SEL,

				 RDMA_MATRIX_INT_MTX_BT601_to_RGB);

		mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, comp,

				   DISP_REG_RDMA_SIZE_CON_0,

				   RDMA_MATRIX_ENABLE);

		mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,

				   comp, DISP_REG_RDMA_SIZE_CON_0,

				   RDMA_MATRIX_INT_MTX_SEL);

	} else {

		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,

				 RDMA_MATRIX_ENABLE, 0);

		mtk_ddp_write_mask(cmdq_pkt, 0, comp,

				   DISP_REG_RDMA_SIZE_CON_0,

				   RDMA_MATRIX_ENABLE);

	}

	mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, DISP_RDMA_MEM_START_ADDR);

	mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, DISP_RDMA_MEM_SRC_PITCH);

	mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, comp,

		      DISP_RDMA_MEM_GMC_SETTING_0);

	mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, comp,

			   DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);



	writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);

	writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);

	writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0);

	rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,

			 RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);

}



static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = {

drivers/gpu/drm/mediatek/mtk_drm_crtc.c

+169 −35
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 


#include <linux/clk.h>

#include <linux/pm_runtime.h>

#include <linux/soc/mediatek/mtk-cmdq.h>



#include <asm/barrier.h>

#include <soc/mediatek/smi.h>
@@ -42,11 +43,20 @@ struct mtk_drm_crtc { 
	struct drm_plane		*planes;

	unsigned int			layer_nr;

	bool				pending_planes;

	bool				pending_async_planes;



#if IS_REACHABLE(CONFIG_MTK_CMDQ)

	struct cmdq_client		*cmdq_client;

	u32				cmdq_event;

#endif



	void __iomem			*config_regs;

	struct mtk_disp_mutex		*mutex;

	unsigned int			ddp_comp_nr;

	struct mtk_ddp_comp		**ddp_comp;



	/* lock for display hardware access */

	struct mutex			hw_lock;

};



struct mtk_crtc_state {
@@ -215,11 +225,12 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 
	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);

	struct mtk_ddp_comp *comp;

	int i, count = 0;

	unsigned int local_index = plane - mtk_crtc->planes;



	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {

		comp = mtk_crtc->ddp_comp[i];

		if (plane->index < (count + mtk_ddp_comp_layer_nr(comp))) {

			*local_layer = plane->index - count;

		if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {

			*local_layer = local_index - count;

			return comp;

		}

		count += mtk_ddp_comp_layer_nr(comp);
@@ -229,6 +240,13 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 
	return NULL;

}



#if IS_REACHABLE(CONFIG_MTK_CMDQ)

static void ddp_cmdq_cb(struct cmdq_cb_data data)

{

	cmdq_pkt_destroy(data.data);

}

#endif



static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)

{

	struct drm_crtc *crtc = &mtk_crtc->base;
@@ -297,7 +315,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 
		if (i == 1)

			mtk_ddp_comp_bgclr_in_on(comp);



		mtk_ddp_comp_config(comp, width, height, vrefresh, bpc);

		mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);

		mtk_ddp_comp_start(comp);

	}
@@ -310,7 +328,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 


		plane_state = to_mtk_plane_state(plane->state);

		comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);

		mtk_ddp_comp_layer_config(comp, local_layer, plane_state);

		if (comp)

			mtk_ddp_comp_layer_config(comp, local_layer,

						  plane_state, NULL);

	}



	return 0;
@@ -325,6 +345,7 @@ err_pm_runtime_put: 
static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)

{

	struct drm_device *drm = mtk_crtc->base.dev;

	struct drm_crtc *crtc = &mtk_crtc->base;

	int i;



	DRM_DEBUG_DRIVER("%s\n", __func__);
@@ -350,9 +371,17 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 
	mtk_disp_mutex_unprepare(mtk_crtc->mutex);



	pm_runtime_put(drm->dev);



	if (crtc->state->event && !crtc->state->active) {

		spin_lock_irq(&crtc->dev->event_lock);

		drm_crtc_send_vblank_event(crtc, crtc->state->event);

		crtc->state->event = NULL;

		spin_unlock_irq(&crtc->dev->event_lock);

	}

}



static void mtk_crtc_ddp_config(struct drm_crtc *crtc)

static void mtk_crtc_ddp_config(struct drm_crtc *crtc,

				struct cmdq_pkt *cmdq_handle)

{

	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);

	struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
@@ -368,7 +397,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) 
	if (state->pending_config) {

		mtk_ddp_comp_config(comp, state->pending_width,

				    state->pending_height,

				    state->pending_vrefresh, 0);

				    state->pending_vrefresh, 0,

				    cmdq_handle);



		state->pending_config = false;

	}
@@ -386,12 +416,84 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) 
			comp = mtk_drm_ddp_comp_for_plane(crtc, plane,

							  &local_layer);



			if (comp)

				mtk_ddp_comp_layer_config(comp, local_layer,

						  plane_state);

							  plane_state,

							  cmdq_handle);

			plane_state->pending.config = false;

		}

		mtk_crtc->pending_planes = false;

	}



	if (mtk_crtc->pending_async_planes) {

		for (i = 0; i < mtk_crtc->layer_nr; i++) {

			struct drm_plane *plane = &mtk_crtc->planes[i];

			struct mtk_plane_state *plane_state;



			plane_state = to_mtk_plane_state(plane->state);



			if (!plane_state->pending.async_config)

				continue;



			comp = mtk_drm_ddp_comp_for_plane(crtc, plane,

							  &local_layer);



			if (comp)

				mtk_ddp_comp_layer_config(comp, local_layer,

							  plane_state,

							  cmdq_handle);

			plane_state->pending.async_config = false;

		}

		mtk_crtc->pending_async_planes = false;

	}

}



static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)

{

#if IS_REACHABLE(CONFIG_MTK_CMDQ)

	struct cmdq_pkt *cmdq_handle;

#endif

	struct drm_crtc *crtc = &mtk_crtc->base;

	struct mtk_drm_private *priv = crtc->dev->dev_private;

	unsigned int pending_planes = 0, pending_async_planes = 0;

	int i;



	mutex_lock(&mtk_crtc->hw_lock);

	for (i = 0; i < mtk_crtc->layer_nr; i++) {

		struct drm_plane *plane = &mtk_crtc->planes[i];

		struct mtk_plane_state *plane_state;



		plane_state = to_mtk_plane_state(plane->state);

		if (plane_state->pending.dirty) {

			plane_state->pending.config = true;

			plane_state->pending.dirty = false;

			pending_planes |= BIT(i);

		} else if (plane_state->pending.async_dirty) {

			plane_state->pending.async_config = true;

			plane_state->pending.async_dirty = false;

			pending_async_planes |= BIT(i);

		}

	}

	if (pending_planes)

		mtk_crtc->pending_planes = true;

	if (pending_async_planes)

		mtk_crtc->pending_async_planes = true;



	if (priv->data->shadow_register) {

		mtk_disp_mutex_acquire(mtk_crtc->mutex);

		mtk_crtc_ddp_config(crtc, NULL);

		mtk_disp_mutex_release(mtk_crtc->mutex);

	}

#if IS_REACHABLE(CONFIG_MTK_CMDQ)

	if (mtk_crtc->cmdq_client) {

		cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);

		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);

		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);

		mtk_crtc_ddp_config(crtc, cmdq_handle);

		cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle);

	}

#endif

	mutex_unlock(&mtk_crtc->hw_lock);

}



int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
@@ -401,7 +503,23 @@ int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 
	struct mtk_ddp_comp *comp;



	comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);

	if (comp)

		return mtk_ddp_comp_layer_check(comp, local_layer, state);

	return 0;

}



void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,

			       struct drm_plane_state *new_state)

{

	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);

	const struct drm_plane_helper_funcs *plane_helper_funcs =

			plane->helper_private;



	if (!mtk_crtc->enabled)

		return;



	plane_helper_funcs->atomic_update(plane, new_state);

	mtk_drm_crtc_hw_config(mtk_crtc);

}



static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
@@ -451,6 +569,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 
	}

	mtk_crtc->pending_planes = true;



	mtk_drm_crtc_hw_config(mtk_crtc);

	/* Wait for planes to be disabled */

	drm_crtc_wait_one_vblank(crtc);
@@ -482,34 +601,16 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 
				      struct drm_crtc_state *old_crtc_state)

{

	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);

	struct mtk_drm_private *priv = crtc->dev->dev_private;

	unsigned int pending_planes = 0;

	int i;



	if (mtk_crtc->event)

		mtk_crtc->pending_needs_vblank = true;

	for (i = 0; i < mtk_crtc->layer_nr; i++) {

		struct drm_plane *plane = &mtk_crtc->planes[i];

		struct mtk_plane_state *plane_state;



		plane_state = to_mtk_plane_state(plane->state);

		if (plane_state->pending.dirty) {

			plane_state->pending.config = true;

			plane_state->pending.dirty = false;

			pending_planes |= BIT(i);

		}

	}

	if (pending_planes)

		mtk_crtc->pending_planes = true;

	if (crtc->state->color_mgmt_changed)

		for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)

		for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {

			mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);



	if (priv->data->shadow_register) {

		mtk_disp_mutex_acquire(mtk_crtc->mutex);

		mtk_crtc_ddp_config(crtc);

		mtk_disp_mutex_release(mtk_crtc->mutex);

			mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);

		}

	mtk_drm_crtc_hw_config(mtk_crtc);

}



static const struct drm_crtc_funcs mtk_crtc_funcs = {
@@ -559,8 +660,12 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) 
	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);

	struct mtk_drm_private *priv = crtc->dev->dev_private;



#if IS_REACHABLE(CONFIG_MTK_CMDQ)

	if (!priv->data->shadow_register && !mtk_crtc->cmdq_client)

#else

	if (!priv->data->shadow_register)

		mtk_crtc_ddp_config(crtc);

#endif

		mtk_crtc_ddp_config(crtc, NULL);



	mtk_drm_finish_page_flip(mtk_crtc);

}
@@ -627,6 +732,8 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, 
	int pipe = priv->num_pipes;

	int ret;

	int i;

	bool has_ctm = false;

	uint gamma_lut_size = 0;



	if (!path)

		return 0;
@@ -677,6 +784,14 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, 
		}



		mtk_crtc->ddp_comp[i] = comp;



		if (comp->funcs) {

			if (comp->funcs->gamma_set)

				gamma_lut_size = MTK_LUT_SIZE;



			if (comp->funcs->ctm_set)

				has_ctm = true;

		}

	}



	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
@@ -697,9 +812,28 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, 
				NULL, pipe);

	if (ret < 0)

		return ret;

	drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);

	drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);

	priv->num_pipes++;



	if (gamma_lut_size)

		drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);

	drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);

	priv->num_pipes++;

	mutex_init(&mtk_crtc->hw_lock);



#if IS_REACHABLE(CONFIG_MTK_CMDQ)

	mtk_crtc->cmdq_client =

			cmdq_mbox_create(dev, drm_crtc_index(&mtk_crtc->base),

					 2000);

	if (IS_ERR(mtk_crtc->cmdq_client)) {

		dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",

			drm_crtc_index(&mtk_crtc->base));

		mtk_crtc->cmdq_client = NULL;

	}

	ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events",

					 drm_crtc_index(&mtk_crtc->base),

					 &mtk_crtc->cmdq_event);

	if (ret)

		dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",

			drm_crtc_index(&mtk_crtc->base));

#endif

	return 0;

}

drivers/gpu/drm/mediatek/mtk_drm_crtc.h

+2 −0
Original line number Diff line number Diff line
@@ -21,5 +21,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, 
			unsigned int path_len);

int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,

			     struct mtk_plane_state *state);

void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,

			       struct drm_plane_state *plane_state);



#endif /* MTK_DRM_CRTC_H */

CRA Git | Maintained and supported by SUSTech CRA and CCSE