Commit 6fac4a3c authored by Ulf Hansson's avatar Ulf Hansson
Browse files

Merge branch 'fixes' into next

parents 9e84a2e6 2a187d03

drivers/mmc/host/sdhci-tegra.c

+1 −1
Original line number Diff line number Diff line
@@ -386,7 +386,7 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 
			misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;

		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)

			misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;

		if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50)

		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)

			clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;

	}

drivers/mmc/host/sdhci.c

+6 −4
Original line number Diff line number Diff line
@@ -4133,10 +4133,12 @@ int sdhci_setup_host(struct sdhci_host *host) 
	if (host->ops->get_min_clock)

		mmc->f_min = host->ops->get_min_clock(host);

	else if (host->version >= SDHCI_SPEC_300) {

		if (host->clk_mul) {

			mmc->f_min = (host->max_clk * host->clk_mul) / 1024;

		if (host->clk_mul)

			max_clk = host->max_clk * host->clk_mul;

		} else

		/*

		 * Divided Clock Mode minimum clock rate is always less than

		 * Programmable Clock Mode minimum clock rate.

		 */

		mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;

	} else

		mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;

CRA Git | Maintained and supported by SUSTech CRA and CCSE