Commit 2a187d03 authored Jan 15, 2020 by Michał Mirosław Committed by Ulf Hansson Jan 20, 2020

mmc: sdhci: fix minimum clock rate for v3 controller



For SDHCIv3+ with programmable clock mode, minimal clock frequency is
still base clock / max(divider). Minimal programmable clock frequency is
always greater than minimal divided clock frequency. Without this patch,
SDHCI uses out-of-spec initial frequency when multiplier is big enough:

mmc1: mmc_rescan_try_freq: trying to init card at 468750 Hz
[for 480 MHz source clock divided by 1024]

The code in sdhci_calc_clk() already chooses a correct SDCLK clock mode.

Fixes: c3ed3877 ("mmc: sdhci: add support for programmable clock mode")
Cc: <stable@vger.kernel.org> # 4f6aa326: mmc: tegra: Only advertise UHS modes if IO regulator is present
Cc: <stable@vger.kernel.org>
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/ffb489519a446caffe7a0a05c4b9372bd52397bb.1579082031.git.mirq-linux@rere.qmqm.pl


Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

parent f571389c

drivers/mmc/host/sdhci.c

+6 −4

Original line number	Diff line number	Diff line
		@@ -3913,10 +3913,12 @@ int sdhci_setup_host(struct sdhci_host *host)
		if (host->ops->get_min_clock)
		mmc->f_min = host->ops->get_min_clock(host);
		else if (host->version >= SDHCI_SPEC_300) {
		if (host->clk_mul) {
		mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
		if (host->clk_mul)
		max_clk = host->max_clk * host->clk_mul;
		} else
		/*
		* Divided Clock Mode minimum clock rate is always less than
		* Programmable Clock Mode minimum clock rate.
		*/
		mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
		} else
		mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;

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