Commit 6fa4e8eb authored by Nishka Dasgupta's avatar Nishka Dasgupta Committed by Greg Kroah-Hartman
Browse files

staging: most: dim2: Remove function dimcb_io_write() 



Remove function dimcb_io_write as all it does is call writel.
Modify calls to dimcb_io_write to writel, flipping the order of the
arguments as required.
Issue found with Coccinelle.

Signed-off-by: default avatarNishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lore.kernel.org/r/20190708064145.3250-3-nishkadg.linux@gmail.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 41e359e6

drivers/staging/most/dim2/dim2.c

+0 −10
Original line number Diff line number Diff line
@@ -128,16 +128,6 @@ bool dim2_sysfs_get_state_cb(void) 
	return state;

}



/**

 * dimcb_io_write - callback from HAL to write value to an I/O register

 * @ptr32: register address

 * @value: value to write

 */

void dimcb_io_write(u32 __iomem *ptr32, u32 value)

{

	writel(value, ptr32);

}



/**

 * dimcb_on_error - callback from HAL to report miscommunication between

 * HDM and HAL

drivers/staging/most/dim2/hal.c

+38 −41
Original line number Diff line number Diff line
@@ -144,13 +144,13 @@ static void free_dbr(int offs, int size) 


static void dim2_transfer_madr(u32 val)

{

	dimcb_io_write(&g.dim2->MADR, val);

	writel(val, &g.dim2->MADR);



	/* wait for transfer completion */

	while ((readl(&g.dim2->MCTL) & 1) != 1)

		continue;



	dimcb_io_write(&g.dim2->MCTL, 0);   /* clear transfer complete */

	writel(0, &g.dim2->MCTL);   /* clear transfer complete */

}



static void dim2_clear_dbr(u16 addr, u16 size)
@@ -160,8 +160,8 @@ static void dim2_clear_dbr(u16 addr, u16 size) 
	u16 const end_addr = addr + size;

	u32 const cmd = bit_mask(MADR_WNR_BIT) | bit_mask(MADR_TB_BIT);



	dimcb_io_write(&g.dim2->MCTL, 0);   /* clear transfer complete */

	dimcb_io_write(&g.dim2->MDAT0, 0);

	writel(0, &g.dim2->MCTL);   /* clear transfer complete */

	writel(0, &g.dim2->MDAT0);



	for (; addr < end_addr; addr++)

		dim2_transfer_madr(cmd | addr);
@@ -178,21 +178,21 @@ static void dim2_write_ctr_mask(u32 ctr_addr, const u32 *mask, const u32 *value) 
{

	enum { MADR_WNR_BIT = 31 };



	dimcb_io_write(&g.dim2->MCTL, 0);   /* clear transfer complete */

	writel(0, &g.dim2->MCTL);   /* clear transfer complete */



	if (mask[0] != 0)

		dimcb_io_write(&g.dim2->MDAT0, value[0]);

		writel(value[0], &g.dim2->MDAT0);

	if (mask[1] != 0)

		dimcb_io_write(&g.dim2->MDAT1, value[1]);

		writel(value[1], &g.dim2->MDAT1);

	if (mask[2] != 0)

		dimcb_io_write(&g.dim2->MDAT2, value[2]);

		writel(value[2], &g.dim2->MDAT2);

	if (mask[3] != 0)

		dimcb_io_write(&g.dim2->MDAT3, value[3]);

		writel(value[3], &g.dim2->MDAT3);



	dimcb_io_write(&g.dim2->MDWE0, mask[0]);

	dimcb_io_write(&g.dim2->MDWE1, mask[1]);

	dimcb_io_write(&g.dim2->MDWE2, mask[2]);

	dimcb_io_write(&g.dim2->MDWE3, mask[3]);

	writel(mask[0], &g.dim2->MDWE0);

	writel(mask[1], &g.dim2->MDWE1);

	writel(mask[2], &g.dim2->MDWE2);

	writel(mask[3], &g.dim2->MDWE3);



	dim2_transfer_madr(bit_mask(MADR_WNR_BIT) | ctr_addr);

}
@@ -357,15 +357,13 @@ static void dim2_configure_channel( 
	dim2_configure_cat(AHB_CAT, ch_addr, type, is_tx ? 0 : 1);



	/* unmask interrupt for used channel, enable mlb_sys_int[0] interrupt */

	dimcb_io_write(&g.dim2->ACMR0,

		       readl(&g.dim2->ACMR0) | bit_mask(ch_addr));

	writel(readl(&g.dim2->ACMR0) | bit_mask(ch_addr), &g.dim2->ACMR0);

}



static void dim2_clear_channel(u8 ch_addr)

{

	/* mask interrupt for used channel, disable mlb_sys_int[0] interrupt */

	dimcb_io_write(&g.dim2->ACMR0,

		       readl(&g.dim2->ACMR0) & ~bit_mask(ch_addr));

	writel(readl(&g.dim2->ACMR0) & ~bit_mask(ch_addr), &g.dim2->ACMR0);



	dim2_clear_cat(AHB_CAT, ch_addr);

	dim2_clear_adt(ch_addr);
@@ -374,7 +372,7 @@ static void dim2_clear_channel(u8 ch_addr) 
	dim2_clear_cdt(ch_addr);



	/* clear channel status bit */

	dimcb_io_write(&g.dim2->ACSR0, bit_mask(ch_addr));

	writel(bit_mask(ch_addr), &g.dim2->ACSR0);

}



/* -------------------------------------------------------------------------- */
@@ -518,20 +516,20 @@ static inline u16 norm_sync_buffer_size(u16 buf_size, u16 bytes_per_frame) 
static void dim2_cleanup(void)

{

	/* disable MediaLB */

	dimcb_io_write(&g.dim2->MLBC0, false << MLBC0_MLBEN_BIT);

	writel(false << MLBC0_MLBEN_BIT, &g.dim2->MLBC0);



	dim2_clear_ctram();



	/* disable mlb_int interrupt */

	dimcb_io_write(&g.dim2->MIEN, 0);

	writel(0, &g.dim2->MIEN);



	/* clear status for all dma channels */

	dimcb_io_write(&g.dim2->ACSR0, 0xFFFFFFFF);

	dimcb_io_write(&g.dim2->ACSR1, 0xFFFFFFFF);

	writel(0xFFFFFFFF, &g.dim2->ACSR0);

	writel(0xFFFFFFFF, &g.dim2->ACSR1);



	/* mask interrupts for all channels */

	dimcb_io_write(&g.dim2->ACMR0, 0);

	dimcb_io_write(&g.dim2->ACMR1, 0);

	writel(0, &g.dim2->ACMR0);

	writel(0, &g.dim2->ACMR1);

}



static void dim2_initialize(bool enable_6pin, u8 mlb_clock)
@@ -539,23 +537,22 @@ static void dim2_initialize(bool enable_6pin, u8 mlb_clock) 
	dim2_cleanup();



	/* configure and enable MediaLB */

	dimcb_io_write(&g.dim2->MLBC0,

		       enable_6pin << MLBC0_MLBPEN_BIT |

	writel(enable_6pin << MLBC0_MLBPEN_BIT |

	       mlb_clock << MLBC0_MLBCLK_SHIFT |

	       g.fcnt << MLBC0_FCNT_SHIFT |

		       true << MLBC0_MLBEN_BIT);

	       true << MLBC0_MLBEN_BIT,

	       &g.dim2->MLBC0);



	/* activate all HBI channels */

	dimcb_io_write(&g.dim2->HCMR0, 0xFFFFFFFF);

	dimcb_io_write(&g.dim2->HCMR1, 0xFFFFFFFF);

	writel(0xFFFFFFFF, &g.dim2->HCMR0);

	writel(0xFFFFFFFF, &g.dim2->HCMR1);



	/* enable HBI */

	dimcb_io_write(&g.dim2->HCTL, bit_mask(HCTL_EN_BIT));

	writel(bit_mask(HCTL_EN_BIT), &g.dim2->HCTL);



	/* configure DMA */

	dimcb_io_write(&g.dim2->ACTL,

		       ACTL_DMA_MODE_VAL_DMA_MODE_1 << ACTL_DMA_MODE_BIT |

		       true << ACTL_SCE_BIT);

	writel(ACTL_DMA_MODE_VAL_DMA_MODE_1 << ACTL_DMA_MODE_BIT |

	       true << ACTL_SCE_BIT, &g.dim2->ACTL);

}



static bool dim2_is_mlb_locked(void)
@@ -566,7 +563,7 @@ static bool dim2_is_mlb_locked(void) 
	u32 const c1 = readl(&g.dim2->MLBC1);

	u32 const nda_mask = (u32)MLBC1_NDA_MASK << MLBC1_NDA_SHIFT;



	dimcb_io_write(&g.dim2->MLBC1, c1 & nda_mask);

	writel(c1 & nda_mask, &g.dim2->MLBC1);

	return (readl(&g.dim2->MLBC1) & mask1) == 0 &&

	       (readl(&g.dim2->MLBC0) & mask0) != 0;

}
@@ -591,7 +588,7 @@ static inline bool service_channel(u8 ch_addr, u8 idx) 
	dim2_write_ctr_mask(ADT + ch_addr, mask, adt_w);



	/* clear channel status bit */

	dimcb_io_write(&g.dim2->ACSR0, bit_mask(ch_addr));

	writel(bit_mask(ch_addr), &g.dim2->ACSR0);



	return true;

}
@@ -777,8 +774,8 @@ static u8 init_ctrl_async(struct dim_channel *ch, u8 type, u8 is_tx, 


void dim_service_mlb_int_irq(void)

{

	dimcb_io_write(&g.dim2->MS0, 0);

	dimcb_io_write(&g.dim2->MS1, 0);

	writel(0, &g.dim2->MS0);

	writel(0, &g.dim2->MS1);

}



/**
@@ -825,7 +822,7 @@ u8 dim_init_async(struct dim_channel *ch, u8 is_tx, u16 ch_address, 
	if (is_tx && !g.atx_dbr.ch_addr) {

		g.atx_dbr.ch_addr = ch->addr;

		dbrcnt_init(ch->addr, ch->dbr_size);

		dimcb_io_write(&g.dim2->MIEN, bit_mask(20));

		writel(bit_mask(20), &g.dim2->MIEN);

	}



	return ret;
@@ -892,7 +889,7 @@ u8 dim_destroy_channel(struct dim_channel *ch) 
		return DIM_ERR_DRIVER_NOT_INITIALIZED;



	if (ch->addr == g.atx_dbr.ch_addr) {

		dimcb_io_write(&g.dim2->MIEN, 0);

		writel(0, &g.dim2->MIEN);

		g.atx_dbr.ch_addr = 0;

	}

drivers/staging/most/dim2/hal.h

+0 −2
Original line number Diff line number Diff line
@@ -97,8 +97,6 @@ bool dim_enqueue_buffer(struct dim_channel *ch, u32 buffer_addr, 


bool dim_detach_buffers(struct dim_channel *ch, u16 buffers_number);



void dimcb_io_write(u32 __iomem *ptr32, u32 value);



void dimcb_on_error(u8 error_id, const char *error_message);



#endif /* _DIM2_HAL_H */

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