Commit 6f73c1e5 authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Tero Kristo
Browse files

arm64: dts: ti: k3-j721e: DMA support 



Add the ringacc and udmap nodes for main and mcu NAVSS.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
parent 515c0340

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

+40 −0
Original line number Diff line number Diff line
@@ -56,6 +56,10 @@ 
		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		dma-coherent;

		dma-ranges;



		ti,sci-dev-id = <199>;



		main_navss_intr: interrupt-controller1 {

			compatible = "ti,sci-intr";
@@ -214,6 +218,42 @@ 
			ti,mbox-num-fifos = <16>;

			interrupt-parent = <&main_navss_intr>;

		};



		main_ringacc: ringacc@3c000000 {

			compatible = "ti,am654-navss-ringacc";

			reg =	<0x0 0x3c000000 0x0 0x400000>,

				<0x0 0x38000000 0x0 0x400000>,

				<0x0 0x31120000 0x0 0x100>,

				<0x0 0x33000000 0x0 0x40000>;

			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";

			ti,num-rings = <1024>;

			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <211>;

			msi-parent = <&main_udmass_inta>;

		};



		main_udmap: dma-controller@31150000 {

			compatible = "ti,j721e-navss-main-udmap";

			reg =	<0x0 0x31150000 0x0 0x100>,

				<0x0 0x34000000 0x0 0x100000>,

				<0x0 0x35000000 0x0 0x100000>;

			reg-names = "gcfg", "rchanrt", "tchanrt";

			msi-parent = <&main_udmass_inta>;

			#dma-cells = <1>;



			ti,sci = <&dmsc>;

			ti,sci-dev-id = <212>;

			ti,ringacc = <&main_ringacc>;



			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */

						<0x0f>, /* TX_HCHAN */

						<0x10>; /* TX_UHCHAN */

			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */

						<0x0b>, /* RX_HCHAN */

						<0x0c>; /* RX_UHCHAN */

			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */

		};

	};



	main_pmx0: pinmux@11c000 {

arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi

+45 −0
Original line number Diff line number Diff line
@@ -225,4 +225,49 @@ 
			compatible = "ti,am3359-adc";

		};

	};



	mcu_navss {

		compatible = "simple-mfd";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		dma-coherent;

		dma-ranges;



		ti,sci-dev-id = <232>;



		mcu_ringacc: ringacc@2b800000 {

			compatible = "ti,am654-navss-ringacc";

			reg =	<0x0 0x2b800000 0x0 0x400000>,

				<0x0 0x2b000000 0x0 0x400000>,

				<0x0 0x28590000 0x0 0x100>,

				<0x0 0x2a500000 0x0 0x40000>;

			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";

			ti,num-rings = <286>;

			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <235>;

			msi-parent = <&main_udmass_inta>;

		};



		mcu_udmap: dma-controller@285c0000 {

			compatible = "ti,j721e-navss-mcu-udmap";

			reg =	<0x0 0x285c0000 0x0 0x100>,

				<0x0 0x2a800000 0x0 0x40000>,

				<0x0 0x2aa00000 0x0 0x40000>;

			reg-names = "gcfg", "rchanrt", "tchanrt";

			msi-parent = <&main_udmass_inta>;

			#dma-cells = <1>;



			ti,sci = <&dmsc>;

			ti,sci-dev-id = <236>;

			ti,ringacc = <&mcu_ringacc>;



			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */

						<0x0f>; /* TX_HCHAN */

			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */

						<0x0b>; /* RX_HCHAN */

			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */

		};

	};

};

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