Commit 6f722509 authored by Kan Liang's avatar Kan Liang Committed by Peter Zijlstra
Browse files

perf/x86/intel: Introduce the fourth fixed counter 



The fourth fixed counter, TOPDOWN.SLOTS, is introduced in Ice Lake to
measure the level 1 TopDown events.

Add MSR address and macros for the new fixed counter, which will be used
in a later patch.

Add comments to explain the event encoding rules for the fixed counters.

Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200723171117.9918-4-kan.liang@linux.intel.com
parent 60a2a271

arch/x86/include/asm/perf_event.h

+20 −3
Original line number Diff line number Diff line
@@ -197,12 +197,24 @@ struct x86_pmu_capability { 
 */



/*

 * All 3 fixed-mode PMCs are configured via this single MSR:

 * All the fixed-mode PMCs are configured via this single MSR:

 */

#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL	0x38d



/*

 * The counts are available in three separate MSRs:

 * There is no event-code assigned to the fixed-mode PMCs.

 *

 * For a fixed-mode PMC, which has an equivalent event on a general-purpose

 * PMC, the event-code of the equivalent event is used for the fixed-mode PMC,

 * e.g., Instr_Retired.Any and CPU_CLK_Unhalted.Core.

 *

 * For a fixed-mode PMC, which doesn't have an equivalent event, a

 * pseudo-encoding is used, e.g., CPU_CLK_Unhalted.Ref and TOPDOWN.SLOTS.

 * The pseudo event-code for a fixed-mode PMC must be 0x00.

 * The pseudo umask-code is 0xX. The X equals the index of the fixed

 * counter + 1, e.g., the fixed counter 2 has the pseudo-encoding 0x0300.

 *

 * The counts are available in separate MSRs:

 */



/* Instr_Retired.Any: */
@@ -213,11 +225,16 @@ struct x86_pmu_capability { 
#define MSR_ARCH_PERFMON_FIXED_CTR1	0x30a

#define INTEL_PMC_IDX_FIXED_CPU_CYCLES	(INTEL_PMC_IDX_FIXED + 1)



/* CPU_CLK_Unhalted.Ref: */

/* CPU_CLK_Unhalted.Ref: event=0x00,umask=0x3 (pseudo-encoding) */

#define MSR_ARCH_PERFMON_FIXED_CTR2	0x30b

#define INTEL_PMC_IDX_FIXED_REF_CYCLES	(INTEL_PMC_IDX_FIXED + 2)

#define INTEL_PMC_MSK_FIXED_REF_CYCLES	(1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)



/* TOPDOWN.SLOTS: event=0x00,umask=0x4 (pseudo-encoding) */

#define MSR_ARCH_PERFMON_FIXED_CTR3	0x30c

#define INTEL_PMC_IDX_FIXED_SLOTS	(INTEL_PMC_IDX_FIXED + 3)

#define INTEL_PMC_MSK_FIXED_SLOTS	(1ULL << INTEL_PMC_IDX_FIXED_SLOTS)



/*

 * We model BTS tracing as another fixed-mode PMC.

 *

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