Commit 60a2a271 authored by Kan Liang's avatar Kan Liang Committed by Peter Zijlstra
Browse files

perf/x86/intel: Name the global status bit in NMI handler 



Magic numbers are used in the current NMI handler for the global status
bit. Use a meaningful name to replace the magic numbers to improve the
readability of the code.

Remove a Tab for all GLOBAL_STATUS_* and INTEL_PMC_IDX_FIXED_BTS macros
to reduce the length of the line.

Suggested-by: default avatarPeter Zijlstra <peterz@infradead.org>
Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200723171117.9918-3-kan.liang@linux.intel.com
parent 75608cb0

arch/x86/events/intel/core.c

+2 −2
Original line number Diff line number Diff line
@@ -2389,7 +2389,7 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) 
	/*

	 * PEBS overflow sets bit 62 in the global status register

	 */

	if (__test_and_clear_bit(62, (unsigned long *)&status)) {

	if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {

		u64 pebs_enabled = cpuc->pebs_enabled;



		handled++;
@@ -2410,7 +2410,7 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) 
	/*

	 * Intel PT

	 */

	if (__test_and_clear_bit(55, (unsigned long *)&status)) {

	if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {

		handled++;

		if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() &&

			perf_guest_cbs->handle_intel_pt_intr))

arch/x86/include/asm/perf_event.h

+12 −10
Original line number Diff line number Diff line
@@ -228,13 +228,15 @@ struct x86_pmu_capability { 
#define INTEL_PMC_IDX_FIXED_BTS			(INTEL_PMC_IDX_FIXED + 16)



#define GLOBAL_STATUS_COND_CHG			BIT_ULL(63)

#define GLOBAL_STATUS_BUFFER_OVF			BIT_ULL(62)

#define GLOBAL_STATUS_BUFFER_OVF_BIT		62

#define GLOBAL_STATUS_BUFFER_OVF		BIT_ULL(GLOBAL_STATUS_BUFFER_OVF_BIT)

#define GLOBAL_STATUS_UNC_OVF			BIT_ULL(61)

#define GLOBAL_STATUS_ASIF			BIT_ULL(60)

#define GLOBAL_STATUS_COUNTERS_FROZEN		BIT_ULL(59)

#define GLOBAL_STATUS_LBRS_FROZEN_BIT		58

#define GLOBAL_STATUS_LBRS_FROZEN		BIT_ULL(GLOBAL_STATUS_LBRS_FROZEN_BIT)

#define GLOBAL_STATUS_TRACE_TOPAPMI			BIT_ULL(55)

#define GLOBAL_STATUS_TRACE_TOPAPMI_BIT		55

#define GLOBAL_STATUS_TRACE_TOPAPMI		BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_BIT)



/*

 * We model guest LBR event tracing as another fixed-mode PMC like BTS.

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