Commit 6dee4829 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: correct UVD/VCE/VCN power status retrieval 



VCN should be used for Vega20 later ASICs while UVD and VCE
are for previous ASICs.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a3ebbdb9

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

+36 −20
Original line number Diff line number Diff line
@@ -3075,6 +3075,21 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a 
	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))

		seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);



	if (adev->asic_type > CHIP_VEGA20) {

		/* VCN clocks */

		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {

			if (!value) {

				seq_printf(m, "VCN: Disabled\n");

			} else {

				seq_printf(m, "VCN: Enabled\n");

				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))

					seq_printf(m, "\t%u MHz (DCLK)\n", value/100);

				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))

					seq_printf(m, "\t%u MHz (VCLK)\n", value/100);

			}

		}

		seq_printf(m, "\n");

	} else {

		/* UVD clocks */

		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {

			if (!value) {
@@ -3099,6 +3114,7 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a 
					seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);

			}

		}

	}



	return 0;

}

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