Commit a3ebbdb9 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: correct Navi10 VCN powergate control (v2) 



No VCN DPM bit check as that's different from VCN PG. Also
no extra check for possible double enablement/disablement
as that's already done by VCN.

v2: check return value of smu_feature_set_enabled

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e21e3581

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

+10 −18
Original line number Diff line number Diff line
@@ -578,28 +578,20 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) 
static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)

{

	int ret = 0;

	struct smu_power_context *smu_power = &smu->smu_power;

	struct smu_power_gate *power_gate = &smu_power->power_gate;



	if (enable && power_gate->uvd_gated) {

		if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {

	if (enable) {

		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);

		if (ret)

			return ret;

		}

		power_gate->uvd_gated = false;

	} else {

		if (!enable && !power_gate->uvd_gated) {

			if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {

		ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);

		if (ret)

			return ret;

	}

			power_gate->uvd_gated = true;

		}

	}



	return 0;

	ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);



	return ret;

}



static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,

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