Commit 6de663fe authored Jul 17, 2015 by Alex Wilson Committed by Michal Simek Jul 31, 2015

ARM: zynq: DT: Add missing interrupt for L2 pl310



Add pl310 interrupt to the Zynq devicetree.

Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

parent 1837649f

arch/arm/boot/dts/zynq-7000.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -139,6 +139,7 @@
		L2: cache-controller@f8f02000 {
		compatible = "arm,pl310-cache";
		reg = <0xF8F02000 0x1000>;
		interrupts = <0 2 4>;
		arm,data-latency = <3 2 2>;
		arm,tag-latency = <2 2 2>;
		cache-unified;

Admin message