dmaengine: xilinx_dma: Fix control reg update in vdma_channel_set_config (6c6de1dd) · Commits · 戴 / test

drivers/dma/xilinx/xilinx_dma.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -68,6 +68,9 @@
		#define XILINX_DMA_DMACR_CIRC_EN BIT(1)
		#define XILINX_DMA_DMACR_RUNSTOP BIT(0)
		#define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5)
		#define XILINX_DMA_DMACR_DELAY_MASK GENMASK(31, 24)
		#define XILINX_DMA_DMACR_FRAME_COUNT_MASK GENMASK(23, 16)
		#define XILINX_DMA_DMACR_MASTER_MASK GENMASK(11, 8)

		#define XILINX_DMA_REG_DMASR 0x0004
		#define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15)
		@@ -2118,8 +2121,10 @@ int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
		chan->config.gen_lock = cfg->gen_lock;
		chan->config.master = cfg->master;

		dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN;
		if (cfg->gen_lock && chan->genlock) {
		dmacr \|= XILINX_DMA_DMACR_GENLOCK_EN;
		dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK;
		dmacr \|= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;
		}

		@@ -2135,11 +2140,13 @@ int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
		chan->config.delay = cfg->delay;

		if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {
		dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK;
		dmacr \|= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;
		chan->config.coalesc = cfg->coalesc;
		}

		if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {
		dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK;
		dmacr \|= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;
		chan->config.delay = cfg->delay;
		}