Commit 68fe2b52 authored Sep 26, 2019 by Radhey Shyam Pandey Committed by Vinod Koul Oct 15, 2019

dmaengine: xilinx_dma: Fix 64-bit simple AXIDMA transfer

In AXI DMA simple mode also pass MSB bits of source and destination
address to xilinx_write function. It fixes simple AXI DMA operation
mode using 64-bit addressing.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Link: https://lore.kernel.org/r/1569495060-18117-2-git-send-email-radhey.shyam.pandey@xilinx.com

Signed-off-by: Vinod Koul <vkoul@kernel.org>

parent bd73dfab

drivers/dma/xilinx/xilinx_dma.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -1354,7 +1354,8 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
		node);
		hw = &segment->hw;

		xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, hw->buf_addr);
		xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR,
		xilinx_prep_dma_addr_t(hw->buf_addr));

		/* Start the transfer */
		dma_ctrl_write(chan, XILINX_DMA_REG_BTT,