Commit 6c0984d5 authored Sep 21, 2018 by Nicholas Kazlauskas Committed by Alex Deucher Oct 09, 2018

drm/amd/display: Raise dispclk value for dce_update_clocks



[Why]

The DISPCLK value was previously requested to be 15% higher for all
ASICS that went through the dce110 bandwidth code path. As part of a
refactoring of dce_clocks and dce110 set_bandwidth this was removed
for power saving considerations.

This changed caused corruption under certain display configurations.
Originally thought to be Vega specific, it was also observed on Polaris.

[How]

The 15% is brought back but its placement differs from the original
patch. This boost should only be enable while DFS bypass is inactive.

This (like the Vega patch) is also a workaround that should be
removed after the root cause is identified.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent a37786ab

drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -664,6 +664,11 @@ static void dce_update_clocks(struct dccg *dccg,
		bool safe_to_lower)
		{
		struct dm_pp_power_level_change_request level_change_req;
		struct dce_dccg *clk_dce = TO_DCE_CLOCKS(dccg);

		/* TODO: Investigate why this is needed to fix display corruption. */
		if (!clk_dce->dfs_bypass_active)
		new_clocks->dispclk_khz = new_clocks->dispclk_khz * 115 / 100;

		level_change_req.power_level = dce_get_required_clocks_state(dccg, new_clocks);
		/* get max clock state from PPLIB */

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