Commit 6a9d10d5 authored by Kevin Hilman's avatar Kevin Hilman
Browse files

Merge tag 'socfpga-dts-updates-for-v3.13' of... 

Merge tag 'socfpga-dts-updates-for-v3.13' of git://git.rocketboards.org/linux-socfpga-next into next/dt

From Dinh Nguyen:
Updates to dts file structure for Altera's SOCFPGA

* Does not include any new bindings or bindings change
* Add dts file for a SOCFPGA with an Arria V FPGA
* Add a clocks property for the TWD timer
* Add support for Terasic SocKit Board which has Cyclone5 FPGA
* From Steffen Trumtrar:
"This series includes some minor cleanups (indentation and clock labels) and
reorders the socfpga dts hierarchy from:
	socfpga.dtsi
	-> socfpga_$board.dts
	-> socfpga_$otherboard.dts
to
	socfpga.dtsi
	-> socfpga_cyclone5.dtsi
	--> socfpga_cyclone5_$board.dts
	--> socfpga_cyclone5_$otherboard.dts
"

* tag 'socfpga-dts-updates-for-v3.13' of git://git.rocketboards.org/linux-socfpga-next

:
  dts: socfpga: Add support for Altera's SOCFPGA Arria V board
  ARM: socfpga: dts: fix s2f_* clock name
  ARM: socfpga: dts: cleanup indentation
  ARM: socfpga: dts: Add support for terasic SoCkit
  ARM: socfpga: dts: Move common nodes to cyclone5 dtsi
  arm: socfpga: Add clock for smp_twd timer

Signed-off-by: default avatarKevin Hilman <khilman@linaro.org>
parents 7a093c74 163a0364

arch/arm/boot/dts/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -217,7 +217,9 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ 
	r8a73a4-ape6evm-reference.dtb \

	sh7372-mackerel.dtb

dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d-reference.dtb

dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \

dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \

	socfpga_cyclone5_socdk.dtb \

	socfpga_cyclone5_sockit.dtb \

	socfpga_vt.dtb

dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \

	spear1340-evb.dtb

arch/arm/boot/dts/socfpga.dtsi

+149 −148
Original line number Diff line number Diff line
@@ -147,7 +147,7 @@ 
							reg = <0x58>;

						};



						cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {

						cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&main_pll>;
@@ -198,7 +198,7 @@ 
							reg = <0x98>;

						};



						s2f_usr1_clk: s2f_usr1_clk {

						h2f_usr1_clk: h2f_usr1_clk {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&periph_pll>;
@@ -235,7 +235,7 @@ 
							reg = <0xD0>;

						};



						s2f_usr2_clk: s2f_usr2_clk {

						h2f_usr2_clk: h2f_usr2_clk {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&sdram_pll>;
@@ -335,14 +335,14 @@ 
					cfg_clk: cfg_clk {

						#clock-cells = <0>;

						compatible = "altr,socfpga-gate-clk";

					clocks = <&cfg_s2f_usr0_clk>;

						clocks = <&cfg_h2f_usr0_clk>;

						clk-gate = <0x60 8>;

					};



				s2f_user0_clk: s2f_user0_clk {

					h2f_user0_clk: h2f_user0_clk {

						#clock-cells = <0>;

						compatible = "altr,socfpga-gate-clk";

					clocks = <&cfg_s2f_usr0_clk>;

						clocks = <&cfg_h2f_usr0_clk>;

						clk-gate = <0x60 9>;

					};
@@ -400,10 +400,10 @@ 
						div-reg = <0xa8 0 24>;

					};



				s2f_user1_clk: s2f_user1_clk {

					h2f_user1_clk: h2f_user1_clk {

						#clock-cells = <0>;

						compatible = "altr,socfpga-gate-clk";

					clocks = <&s2f_usr1_clk>;

						clocks = <&h2f_usr1_clk>;

						clk-gate = <0xa0 7>;

					};
@@ -473,6 +473,7 @@ 
			compatible = "arm,cortex-a9-twd-timer";

			reg = <0xfffec600 0x100>;

			interrupts = <1 13 0xf04>;

			clocks = <&mpu_periph_clk>;

		};



		timer0: timer0@ffc08000 {

arch/arm/boot/dts/socfpga_arria5.dtsi

0 → 100644
+58 −0
Original line number Diff line number Diff line 
/*

 *  Copyright (C) 2013 Altera Corporation <www.altera.com>

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */



/dts-v1/;

/include/ "socfpga.dtsi"



/ {

	soc {

		clkmgr@ffd04000 {

			clocks {

				osc1 {

					clock-frequency = <25000000>;

				};

			};

		};



		serial0@ffc02000 {

			clock-frequency = <100000000>;

		};



		serial1@ffc03000 {

			clock-frequency = <100000000>;

		};



		sysmgr@ffd08000 {

			cpu1-start-addr = <0xffd080c4>;

		};



		timer0@ffc08000 {

			clock-frequency = <100000000>;

		};



		timer1@ffc09000 {

			clock-frequency = <100000000>;

		};



		timer2@ffd00000 {

			clock-frequency = <25000000>;

		};



		timer3@ffd01000 {

			clock-frequency = <25000000>;

		};

	};

};

arch/arm/boot/dts/socfpga_arria5_socdk.dts

0 → 100644
+40 −0
Original line number Diff line number Diff line 
/*

 *  Copyright (C) 2013 Altera Corporation <www.altera.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



/include/ "socfpga_arria5.dtsi"



/ {

	model = "Altera SOCFPGA Arria V SoC Development Kit";

	compatible = "altr,socfpga-arria5", "altr,socfpga";



	chosen {

		bootargs = "console=ttyS0,115200";

	};



	memory {

		name = "memory";

		device_type = "memory";

		reg = <0x0 0x40000000>; /* 1GB */

	};



	aliases {

		/* this allow the ethaddr uboot environmnet variable contents

		* to be added to the gmac1 device tree blob.

		*/

		ethernet0 = &gmac1;

	};

};

arch/arm/boot/dts/socfpga_cyclone5.dts→arch/arm/boot/dts/socfpga_cyclone5.dtsi

+0 −20
Original line number Diff line number Diff line
@@ -19,26 +19,6 @@ 
/include/ "socfpga.dtsi"



/ {

	model = "Altera SOCFPGA Cyclone V";

	compatible = "altr,socfpga-cyclone5", "altr,socfpga";



	chosen {

		bootargs = "console=ttyS0,57600";

	};



	memory {

		name = "memory";

		device_type = "memory";

		reg = <0x0 0x40000000>; /* 1GB */

	};



	aliases {

		/* this allow the ethaddr uboot environmnet variable contents

		 * to be added to the gmac1 device tree blob.

		 */

		ethernet0 = &gmac1;

	};



	soc {

		clkmgr@ffd04000 {

			clocks {

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