Commit 69f7be1c authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro 



Currently the PINMUX_CFG_REG_VAR() macro must be followed by
initialization data, specifying all enum IDs.  Hence the macro itself
does not know anything about the enum IDs, preventing the macro from
performing any validation on it.

Make the macro accept the enum IDs as a parameter, and update all users.
Note that array data enclosed by curly braces cannot be passed to a
macro as a parameter, hence both the register field widths and the enum
IDs are wrapped using the GROUP() macro.

No functional changes.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent efca8da0

drivers/pinctrl/sh-pfc/pfc-emev2.c

+29 −18
Original line number Diff line number Diff line
@@ -1609,8 +1609,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		))

	},

	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,

			1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

			1, 1, 1, 1, 2, 2, 2, 2, 2, 2) {

			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,

				   2, 2),

			     GROUP(

		/* 31 - 12 */

		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1624,11 +1626,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* 1 - 0 */

		FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,

			1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

			1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {

			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 2),

			     GROUP(

		/* 31 - 2 */

		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1636,11 +1640,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* 1 - 0 */

		FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,

			1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

			1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {

			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 2),

			     GROUP(

		/* 31 - 2 */

		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1648,11 +1654,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* 1 - 0 */

		FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,

			1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

			2, 2, 2, 2, 2, 2, 2, 2) {

			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2),

			     GROUP(

		/* 31 - 14 */

		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1673,11 +1680,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,

		/* 1 - 0 */

		FN_SEL_AB_1_0_00, 0, FN_SEL_AB_1_0_10, 0,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,

			1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

			1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2) {

			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,

				   2, 2, 2),

			     GROUP(

		/* 31 - 10 */

		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1692,11 +1701,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, 0, 0,

		/* 1 - 0 */

		FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, 0, 0,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,

			1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

			1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {

			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 2),

			     GROUP(

		/* 31 - 2 */

		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1704,7 +1715,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* 1 - 0 */

		FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0,

		}

		))

	},

	{ },

};

drivers/pinctrl/sh-pfc/pfc-r8a77470.c

+66 −45
Original line number Diff line number Diff line
@@ -2746,7 +2746,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_5_0_FN, FN_IP13_31_28, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP0_31_28 [4] */

		FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0,
@@ -2770,10 +2771,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0, 0, 0,

		/* IP0_3_0 [4] */

		FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, }

		0, 0, 0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP1_31_28 [4] */

		FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0,
@@ -2797,10 +2799,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0, 0, 0,

		/* IP1_3_0 [4] */

		FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, }

		0, 0, 0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP2_31_28 [4] */

		FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0,
@@ -2824,10 +2827,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP2_3_0 [4] */

		FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, }

		0, 0, 0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP3_31_28 [4] */

		FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		0, 0,
@@ -2852,10 +2856,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		/* IP3_3_0 [4] */

		FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B,

		0, FN_AVB_AVTP_CAPTURE_A,

		0, 0, 0, 0, 0, 0, 0, 0, 0, }

		0, 0, 0, 0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP4_31_28 [4] */

		FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0,

		0, 0, 0, 0, 0, 0, 0, 0,
@@ -2879,10 +2884,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0, 0, 0,

		/* IP4_3_0 [4] */

		FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, 0, }

		0, 0, 0, 0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP5_31_28 [4] */

		FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14,  0, 0, 0,

		0, 0, 0, 0, 0, 0,
@@ -2906,10 +2912,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0, 0, 0,

		/* IP5_3_0 [4] */

		FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0,

		0, 0, 0, 0, 0, 0, 0, 0, }

		0, 0, 0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP6_31_28 [4] */

		FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0,

		0, 0, 0, 0, 0, 0, 0,
@@ -2933,10 +2940,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP6_3_0 [4] */

		FN_DU0_DG7, 0, FN_HTX1_C, 0,  FN_PWM6_B, 0, FN_A15,

		0, 0, 0, 0, 0, 0, 0, 0, 0, }

		0, 0, 0, 0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP7_31_28 [4] */

		FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0,
@@ -2960,10 +2968,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0,

		/* IP7_3_0 [4] */

		FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0,

		0, 0, 0, 0, 0, 0, 0, }

		0, 0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP8_31_28 [4] */

		FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0,
@@ -2987,10 +2996,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0, 0,

		/* IP8_3_0 [4] */

		FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0,

		0, 0, 0, 0, }

		0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP9_31_28 [4] */

		FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0,
@@ -3014,10 +3024,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0,

		/* IP9_3_0 [4] */

		FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, }

		0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP10_31_28 [4] */

		FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0,

		FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3042,10 +3053,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0, 0,

		/* IP10_3_0 [4] */

		FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, }

		0, 0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP11_31_28 [4] */

		FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3073,10 +3085,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0, 0, 0,

		/* IP11_3_0 [4] */

		FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B,

		FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, }

		FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP12_31_28 [4] */

		FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3100,10 +3113,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP12_3_0 [4] */

		FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, }

		0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP13_31_28 [4] */

		FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0,
@@ -3128,10 +3142,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP13_3_0 [4] */

		FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, }

		0, 0, 0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP14_31_28 [4] */

		FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,

		FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3155,10 +3170,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP14_3_0 [4] */

		FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, }

		0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP15_31_28 [4] */

		FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0,

		0, 0, 0, 0, 0, 0,
@@ -3182,10 +3198,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP15_3_0 [4] */

		FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0,

		FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, }

		FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP16_31_28 [4] */

		FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0,

		FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3210,10 +3227,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP16_3_0 [4] */

		FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0,

		0, 0, 0, 0, 0, 0, }

		0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP17_31_28 [4] */

		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP17_27_24 [4] */
@@ -3236,11 +3254,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP17_3_0 [4] */

		FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1,

		FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, }

		FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,

			     1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1, 3, 3,

				 1, 2, 3, 3, 1) {

			     GROUP(1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1,

				   3, 3, 1, 2, 3, 3, 1),

			     GROUP(

		/* RESERVED [1] */

		0, 0,

		/* RESERVED [1] */
@@ -3283,11 +3302,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,

		FN_SEL_I2C00_4, 0, 0, 0,

		/* SEL_AVB [1] */

		FN_SEL_AVB_0, FN_SEL_AVB_1, }

		FN_SEL_AVB_0, FN_SEL_AVB_1, ))

	},

	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,

			     1, 3, 3, 2, 2, 1, 2, 2,

			     2, 1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 1) {

			     GROUP(1, 3, 3, 2, 2, 1, 2, 2, 2, 1, 1, 1,

				   1, 1, 2, 1, 1, 2, 2, 1),

			     GROUP(

		/* SEL_SCIFCLK [1] */

		FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,

		/* SEL_SCIF5 [3] */
@@ -3329,11 +3349,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		/* SEL_HSCIF1 [2] */

		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0,

		/* SEL_HSCIF0 [1] */

		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,}

		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, ))

	},

	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,

			     1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) {

			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,

				   2, 2, 2, 2, 2, 2, 2, 2, 2),

			     GROUP(

		/* RESERVED [1] */

		0, 0,

		/* RESERVED [1] */
@@ -3375,7 +3396,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		/* SEL_SSI1 [2] */

		FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,

		/* SEL_SSI0 [2] */

		FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, }

		FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, ))

	},

	{ },

};

drivers/pinctrl/sh-pfc/pfc-r8a7778.c

+49 −32
Original line number Diff line number Diff line
@@ -2276,8 +2276,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	},



	{ PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,

			     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

			     1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) {

			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 3, 4, 3, 3, 2),

			     GROUP(

		/* IP0_31 [1] */

		0,	0,

		/* IP0_30 [1] */
@@ -2328,10 +2329,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_TX2_E,	FN_SDA2_B,		0,		0,

		/* IP0_1_0 [2] */

		FN_PRESETOUT,	0,	FN_PWM1,	0,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,

			     1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) {

			     GROUP(1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3,

				   3, 1, 1),

			     GROUP(

		/* IP1_31 [1] */

		0,	0,

		/* IP1_30 [1] */
@@ -2371,11 +2374,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_A21,		FN_HSPI_CLK1_B,

		/* IP1_0 [1] */

		FN_A20,		FN_HSPI_CS1_B,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,

			     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

			     1, 1, 1, 1, 3, 2, 3, 3, 3, 3) {

			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 3, 2, 3, 3, 3, 3),

			     GROUP(

		/* IP2_31 [1] */

		FN_MLB_CLK,	FN_IRQ1_A,

		/* IP2_30 [1] */
@@ -2423,11 +2427,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		/* IP2_2_0 [3] */

		FN_SD1_CLK_A,	FN_MMC_CLK,	0,	FN_ATACS00,

		FN_EX_CS2,	0,		0,	0,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,

			     1, 1, 1, 1, 1, 3, 3, 2,

			     3, 3, 3, 2, 3, 3, 2) {

			     GROUP(1, 1, 1, 1, 1, 3, 3, 2, 3, 3, 3, 2,

				   3, 3, 2),

			     GROUP(

		/* IP3_31 [1] */

		FN_DU0_DR6,	FN_LCDOUT6,

		/* IP3_30 [1] */
@@ -2465,10 +2470,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_SDSELF_B,	0,		0,		0,

		/* IP3_1_0 [2] */

		FN_MLB_SIG,	FN_RX5_B,	FN_SDA3_A,	FN_IRQ2_A,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,

			     1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) {

			     GROUP(1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1,

				   3, 3, 1),

			     GROUP(

		/* IP4_31 [1] */

		0,	0,

		/* IP4_30_29 [2] */
@@ -2507,10 +2514,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_TX1_D,	FN_CAN0_TX_A,	FN_ADICHS0,	0,

		/* IP4_0 [1] */

		FN_DU0_DR7,	FN_LCDOUT7,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,

			     1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) {

			     GROUP(1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1,

				   1, 2, 2, 2),

			     GROUP(



		/* IP5_31 [1] */

		0, 0,
@@ -2551,11 +2560,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_VI1_DATA10_B,	FN_DU0_DB6,	FN_LCDOUT22,	0,

		/* IP5_1_0 [2] */

		FN_VI0_R5_B,		FN_DU0_DB5,	FN_LCDOUT21,	0,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,

			     2, 2, 2, 2, 2, 1, 2, 2, 1, 2,

			     1, 2, 1, 1, 1, 1, 2, 3, 2) {

			     GROUP(2, 2, 2, 2, 2, 1, 2, 2, 1, 2, 1, 2,

				   1, 1, 1, 1, 2, 3, 2),

			     GROUP(

		/* IP6_31_30 [2] */

		FN_SD0_DAT2,	0,	FN_SUB_TDI,	0,

		/* IP6_29_28 [2] */
@@ -2602,10 +2612,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		/* IP6_1_0 [2] */

		FN_SSI_SCK6,		FN_HSPI_RX2_A,

		FN_FMCLK_B,		FN_CAN1_TX_B,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,

			     3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) {

			     GROUP(3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2),

			     GROUP(



		/* IP7_31_29 [3] */

		FN_VI0_HSYNC,	FN_SD2_CD_B,	FN_VI1_DATA2,	FN_DU1_DR2,
@@ -2641,10 +2652,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_SD0_CD,	0,		FN_TX5_A,	0,

		/* IP7_1_0 [2] */

		FN_SD0_DAT3,	0,		FN_IRQ1_B,	0,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,

			     1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) {

			     GROUP(1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3),

			     GROUP(

		/* IP8_31 [1] */

		0, 0,

		/* IP8_30 [1] */
@@ -2681,10 +2693,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		/* IP8_2_0 [3] */

		FN_VI0_VSYNC,		FN_SD2_WP_B,	FN_VI1_DATA3,	FN_DU1_DR3,

		0,			FN_HSPI_TX1_A,	FN_TX3_B,	0,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,

			     1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {

			     GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),

			     GROUP(

		/* IP9_31 [1] */

		0, 0,

		/* IP9_30 [1] */
@@ -2723,10 +2736,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		/* IP9_2_0 [3] */

		FN_VI0_G4,	FN_SD2_DAT0_B,	FN_VI1_DATA6,	FN_DU1_DR6,

		0,		FN_HRTS1_B,	0,		0,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,

			     1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) {

			     GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4,

				   3, 3, 3),

			     GROUP(



		/* IP10_31 [1] */

		0, 0,
@@ -2772,11 +2787,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_ATARD1,	FN_ETH_MDC,

		FN_SDA1_B,	0,

		0,		0,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,

			     1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,

			     1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {

			     GROUP(1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,

				   1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),

			     GROUP(



		/* SEL 31  [1] */

		0, 0,
@@ -2835,11 +2851,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_SEL_WAIT2_A,		FN_SEL_WAIT2_B,

		/* SEL_0 (WAIT1) [1] */

		FN_SEL_WAIT1_A,		FN_SEL_WAIT1_B,

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,

			     1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1,

			     1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) {

			     GROUP(1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1),

			     GROUP(



		/* SEL_31 [1] */

		0, 0,
@@ -2899,7 +2916,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_SEL_I2C2_C,		0,

		/* SEL_0 (I2C1) [1] */

		FN_SEL_I2C1_A,		FN_SEL_I2C1_B,

		}

		))

	},

	{ },

};

drivers/pinctrl/sh-pfc/pfc-r8a7779.c

+53 −36
Original line number Diff line number Diff line
@@ -3377,7 +3377,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	},



	{ PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,

			     1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3) {

			     GROUP(1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3),

			     GROUP(

		/* IP0_31 [1] */

		0, 0,

		/* IP0_30_28 [3] */
@@ -3412,10 +3413,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,

		/* IP0_2_0 [3] */

		FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,

		FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }

		FN_SCIF_CLK, FN_TCLK0_C, 0, 0 ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,

			     3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2) {

			     GROUP(3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2),

			     GROUP(

		/* IP1_31_29 [3] */

		0, 0, 0, 0, 0, 0, 0, 0,

		/* IP1_28_25 [4] */
@@ -3450,10 +3452,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		/* IP1_3_2 [2] */

		FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0,

		/* IP1_1_0 [2] */

		FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 }

		FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,

			     1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4) {

			     GROUP(1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4),

			     GROUP(

		/* IP2_31 [1] */

		0, 0,

		/* IP2_30_28 [3] */
@@ -3496,11 +3499,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,

		FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,

		FN_CC5_STATE27, FN_CC5_STATE35, 0, 0,

		0, 0, 0, 0 }

		0, 0, 0, 0 ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,

			     3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1,

			     1, 3, 3, 1, 1, 1, 1, 1, 1, 3) {

			     GROUP(3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1, 1,

				   3, 3, 1, 1, 1, 1, 1, 1, 3),

			     GROUP(

	    /* IP3_31_29 [3] */

	    FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C,

	    FN_SCL2_C, FN_REMOCON, 0, 0,
@@ -3547,11 +3551,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	    FN_DU0_DG2, FN_LCDOUT10,

	    /* IP3_2_0 [3] */

	    FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,

	    FN_AUDATA3, 0, 0, 0 }

	    FN_AUDATA3, 0, 0, 0 ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,

			     3, 1, 1, 1, 1, 1, 1, 3, 3,

			     1, 1, 1, 1, 1, 1, 3, 3, 3, 2) {

			     GROUP(3, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,

				   1, 1, 1, 3, 3, 3, 2),

			     GROUP(

	    /* IP4_31_29 [3] */

	    FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,

	    FN_TX5, FN_SCK0_D, 0, 0,
@@ -3595,11 +3600,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	    FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,

	    FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0,

	    /* IP4_1_0 [2] */

	    FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C }

	    FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,

			     1, 2, 1, 4, 3, 4, 2, 2,

			     2, 2, 1, 1, 1, 1, 1, 1, 3) {

			     GROUP(1, 2, 1, 4, 3, 4, 2, 2, 2, 2, 1, 1,

				   1, 1, 1, 1, 3),

			     GROUP(

	    /* IP5_31 [1] */

	    0, 0,

	    /* IP5_30_29 [2] */
@@ -3641,10 +3647,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	    FN_DU1_DB2, FN_VI2_R4,

	    /* IP5_2_0 [3] */

	    FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,

	    FN_RX5, FN_RTS0_D_TANS_D, 0, 0 }

	    FN_RX5, FN_RTS0_D_TANS_D, 0, 0 ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,

			     1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 2, 2, 2) {

			     GROUP(1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2,

				   2, 2, 2),

			     GROUP(

	    /* IP6_31 [1] */

	    0, 0,

	    /* IP6_30_29 [2] */
@@ -3678,10 +3686,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	    /* IP6_3_2 [2] */

	    FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0,

	    /* IP6_1_0 [2] */

	    FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 }

	    FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,

			     1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2) {

			     GROUP(1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,

				   3, 2, 2),

			     GROUP(

	    /* IP7_31 [1] */

	    0, 0,

	    /* IP7_30_29 [2] */
@@ -3714,10 +3724,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	    /* IP7_3_2 [2] */

	    FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,

	    /* IP7_1_0 [2] */

	    FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B }

	    FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,

			     1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4) {

			     GROUP(1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4),

			     GROUP(

	    /* IP8_31 [1] */

	    0, 0,

	    /* IP8_30_28 [3] */
@@ -3757,11 +3768,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	    FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,

	    FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,

	    FN_CC5_STATE36, 0, 0, 0,

	    0, 0, 0, 0 }

	    0, 0, 0, 0 ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,

			     2, 2, 2, 2, 2, 3, 3, 2, 2,

			     2, 2, 1, 1, 1, 1, 2, 2) {

			     GROUP(2, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 1,

				   1, 1, 1, 2, 2),

			     GROUP(

	    /* IP9_31_30 [2] */

	    0, 0, 0, 0,

	    /* IP9_29_28 [2] */
@@ -3797,10 +3809,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	    /* IP9_3_2 [2] */

	    FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0,

	    /* IP9_1_0 [2] */

	    FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 }

	    FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,

			     3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3) {

			     GROUP(3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3),

			     GROUP(

	    /* IP10_31_29 [3] */

	    FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK,

	    FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0,
@@ -3832,10 +3845,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	    FN_DACK0_C, FN_DRACK0_C, 0, 0,

	    /* IP10_2_0 [3] */

	    FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,

	    FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 }

	    FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,

			     2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {

			     GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),

			     GROUP(

	    /* IP11_31_30 [2] */

	    0, 0, 0, 0,

	    /* IP11_29_27 [3] */
@@ -3867,10 +3881,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	    FN_ADICS_B_SAMP_B, 0, 0, 0,

	    /* IP11_2_0 [3] */

	    FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,

	    FN_ADICLK_B, 0, 0, 0 }

	    FN_ADICLK_B, 0, 0, 0 ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,

			     4, 4, 4, 2, 3, 3, 3, 3, 3, 3) {

			     GROUP(4, 4, 4, 2, 3, 3, 3, 3, 3, 3),

			     GROUP(

	    /* IP12_31_28 [4] */

	    0, 0, 0, 0, 0, 0, 0, 0,

	    0, 0, 0, 0, 0, 0, 0, 0,
@@ -3899,11 +3914,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	    FN_SCL1_C, FN_HTX0_B, 0, 0,

	    /* IP12_2_0 [3] */

	    FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,

	    FN_SCK2, FN_HSCK0_B, 0, 0 }

	    FN_SCK2, FN_HSCK0_B, 0, 0 ))

	},

	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32,

			     2, 2, 3, 3, 2, 2, 2, 2, 2,

			     1, 1, 1, 1, 1, 1, 1, 2, 1, 2) {

			     GROUP(2, 2, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1,

				   1, 1, 1, 1, 2, 1, 2),

			     GROUP(

	    /* SEL_SCIF5 [2] */

	    FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,

	    /* SEL_SCIF4 [2] */
@@ -3943,11 +3959,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	    /* SEL_EXBUS1 [1] */

	    FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,

	    /* SEL_EXBUS0 [2] */

	    FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 }

	    FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 ))

	},

	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,

			     2, 2, 2, 2, 1, 1, 1, 3, 1,

			     2, 2, 2, 2, 1, 1, 2, 1, 2, 2) {

			     GROUP(2, 2, 2, 2, 1, 1, 1, 3, 1, 2, 2, 2,

				   2, 1, 1, 2, 1, 2, 2),

			     GROUP(

	    /* SEL_TMU1 [2] */

	    FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0,

	    /* SEL_TMU0 [2] */
@@ -3986,7 +4003,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	    /* SEL_I2C2 [2] */

	    FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,

	    /* SEL_I2C1 [2] */

	    FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }

	    FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 ))

	},

	{ },

};

drivers/pinctrl/sh-pfc/pfc-r8a7790.c

+63 −44

File changed.

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