Commit efca8da0 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro 



Currently the PINMUX_CFG_REG() macro must be followed by initialization
data, specifying all enum IDs.  Hence the macro itself does not know
anything about the enum IDs, preventing the macro from performing any
validation on it.

Make the macro accept the enum IDs as a parameter, and update all users.
Note that array data enclosed by curly braces cannot be passed to a
macro as a parameter, hence the enum IDs are wrapped using a new macro
GROUPS().

No functional changes.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 01ff33a3

drivers/pinctrl/sh-pfc/pfc-emev2.c

+10 −10
Original line number Diff line number Diff line
@@ -1433,7 +1433,7 @@ static const struct sh_pfc_function pinmux_functions[] = { 
};



static const struct pinmux_cfg_reg pinmux_config_regs[] = {

	{ PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1) {

	{ PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1, GROUP(

		0, PORT31_FN,				/* PIN: J18  */

		0, PORT30_FN,				/* PIN: H18  */

		0, PORT29_FN,				/* PIN: G18  */
@@ -1466,9 +1466,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_JT_SEL, PORT2_FN,			/* PIN: V9   */

		0, PORT1_FN,				/* PIN: U10  */

		0, PORT0_FN,				/* PIN: V10  */

		}

		))

	},

	{ PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1) {

	{ PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1, GROUP(

		FN_SDI1_CMD, PORT63_FN,			/* PIN: AC21 */

		FN_SDI1_CKI, PORT62_FN,			/* PIN: AA23 */

		FN_SDI1_CKO, PORT61_FN,			/* PIN: AB22 */
@@ -1501,9 +1501,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_LCD3_R2, PORT34_FN,			/* PIN: A19  */

		FN_LCD3_R1, PORT33_FN,			/* PIN: B20  */

		FN_LCD3_R0, PORT32_FN,			/* PIN: A20  */

		}

		))

	},

	{ PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1) {

	{ PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1, GROUP(

		FN_AB_1_0_PORT95, PORT95_FN,		/* PIN: L21  */

		FN_AB_1_0_PORT94, PORT94_FN,		/* PIN: K21  */

		FN_AB_1_0_PORT93, PORT93_FN,		/* PIN: J21  */
@@ -1536,9 +1536,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_SDI1_DATA2, PORT66_FN,		/* PIN: AB19 */

		FN_SDI1_DATA1, PORT65_FN,		/* PIN: AB20 */

		FN_SDI1_DATA0, PORT64_FN,		/* PIN: AB21 */

		}

		))

	},

	{ PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1) {

	{ PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1, GROUP(

		FN_NTSC_DATA4, PORT127_FN,		/* PIN: T20  */

		FN_NTSC_DATA3, PORT126_FN,		/* PIN: R18  */

		FN_NTSC_DATA2, PORT125_FN,		/* PIN: R20  */
@@ -1571,9 +1571,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_AB_9_8_PORT98, PORT98_FN,		/* PIN: M20  */

		FN_AB_9_8_PORT97, PORT97_FN,		/* PIN: N21  */

		FN_AB_A20, PORT96_FN,			/* PIN: M21  */

		}

		))

	},

	{ PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1) {

	{ PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1, GROUP(

		0, 0,

		FN_UART_1_0_PORT158, PORT158_FN,	/* PIN: AB10 */

		FN_UART_1_0_PORT157, PORT157_FN,	/* PIN: AA10 */
@@ -1606,7 +1606,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_NTSC_DATA7, PORT130_FN,		/* PIN: U18  */

		FN_NTSC_DATA6, PORT129_FN,		/* PIN: U20  */

		FN_NTSC_DATA5, PORT128_FN,		/* PIN: T18  */

		}

		))

	},

	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,

			1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

drivers/pinctrl/sh-pfc/pfc-r8a73a4.c

+10 −10
Original line number Diff line number Diff line
@@ -2284,7 +2284,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	PORTCR(328, 0xe6053148),

	PORTCR(329, 0xe6053149),



	{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {

	{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(

			MSEL1CR_31_0, MSEL1CR_31_1,

			0, 0,

			0, 0,
@@ -2317,9 +2317,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
			MSEL1CR_02_0, MSEL1CR_02_1,

			MSEL1CR_01_0, MSEL1CR_01_1,

			MSEL1CR_00_0, MSEL1CR_00_1,

		}

		))

	},

	{ PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {

	{ PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(

			MSEL3CR_31_0, MSEL3CR_31_1,

			0, 0,

			0, 0,
@@ -2352,9 +2352,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
			0, 0,

			MSEL3CR_01_0, MSEL3CR_01_1,

			MSEL3CR_00_0, MSEL3CR_00_1,

			}

			))

	},

	{ PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {

	{ PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(

			0, 0,

			MSEL4CR_30_0, MSEL4CR_30_1,

			MSEL4CR_29_0, MSEL4CR_29_1,
@@ -2387,9 +2387,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
			0, 0,

			MSEL4CR_01_0, MSEL4CR_01_1,

			0, 0,

		}

		))

	},

	{ PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {

	{ PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1, GROUP(

			MSEL5CR_31_0, MSEL5CR_31_1,

			MSEL5CR_30_0, MSEL5CR_30_1,

			MSEL5CR_29_0, MSEL5CR_29_1,
@@ -2422,9 +2422,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
			0, 0,

			0, 0,

			0, 0,

		}

		))

	},

	{ PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {

	{ PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1, GROUP(

			0, 0,

			0, 0,

			0, 0,
@@ -2457,7 +2457,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
			0, 0,

			MSEL8CR_01_0, MSEL8CR_01_1,

			MSEL8CR_00_0, MSEL8CR_00_1,

		}

		))

	},

	{ },

};

drivers/pinctrl/sh-pfc/pfc-r8a7740.c

+8 −8
Original line number Diff line number Diff line
@@ -3436,7 +3436,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	PORTCR(210,	0xe60530d2), /* PORT210CR */

	PORTCR(211,	0xe60530d3), /* PORT211CR */



	{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {

	{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(

			MSEL1CR_31_0,	MSEL1CR_31_1,

			MSEL1CR_30_0,	MSEL1CR_30_1,

			MSEL1CR_29_0,	MSEL1CR_29_1,
@@ -3461,9 +3461,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
			MSEL1CR_2_0,	MSEL1CR_2_1,

			0, 0,

			MSEL1CR_0_0,	MSEL1CR_0_1,

		}

		))

	},

	{ PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {

	{ PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1, GROUP(

			0, 0, 0, 0, 0, 0, 0, 0,

			0, 0, 0, 0, 0, 0, 0, 0,

			0, 0, 0, 0, 0, 0, 0, 0,
@@ -3474,9 +3474,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
			MSEL3CR_6_0,	MSEL3CR_6_1,

			0, 0, 0, 0, 0, 0, 0, 0,

			0, 0, 0, 0,

			}

			))

	},

	{ PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {

	{ PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1, GROUP(

			0, 0, 0, 0, 0, 0, 0, 0,

			0, 0, 0, 0, 0, 0, 0, 0,

			0, 0, 0, 0, 0, 0, 0, 0,
@@ -3493,9 +3493,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
			0, 0, 0, 0,

			MSEL4CR_1_0,	MSEL4CR_1_1,

			0, 0,

		}

		))

	},

	{ PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {

	{ PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1, GROUP(

			MSEL5CR_31_0,	MSEL5CR_31_1,

			MSEL5CR_30_0,	MSEL5CR_30_1,

			MSEL5CR_29_0,	MSEL5CR_29_1,
@@ -3528,7 +3528,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
			MSEL5CR_2_0,	MSEL5CR_2_1,

			0, 0,

			MSEL5CR_0_0,	MSEL5CR_0_1,

		}

		))

	},

	{ },

};

drivers/pinctrl/sh-pfc/pfc-r8a77470.c

+12 −12
Original line number Diff line number Diff line
@@ -2541,7 +2541,7 @@ static const struct sh_pfc_function pinmux_functions[] = { 
};



static const struct pinmux_cfg_reg pinmux_config_regs[] = {

	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {

	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,
@@ -2573,9 +2573,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_0_3_FN, FN_USB1_OVC,

		GP_0_2_FN, FN_USB1_PWEN,

		GP_0_1_FN, FN_USB0_OVC,

		GP_0_0_FN, FN_USB0_PWEN, }

		GP_0_0_FN, FN_USB0_PWEN, ))

	},

	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {

	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,
@@ -2607,9 +2607,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_1_3_FN, FN_IP1_23_20,

		GP_1_2_FN, FN_IP1_19_16,

		GP_1_1_FN, FN_IP1_15_12,

		GP_1_0_FN, FN_IP1_11_8, }

		GP_1_0_FN, FN_IP1_11_8, ))

	},

	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {

	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(

		GP_2_31_FN, FN_IP8_3_0,

		GP_2_30_FN, FN_IP7_31_28,

		GP_2_29_FN, FN_IP7_27_24,
@@ -2641,9 +2641,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_2_3_FN, FN_IP4_19_16,

		GP_2_2_FN, FN_IP4_15_12,

		GP_2_1_FN, FN_IP4_11_8,

		GP_2_0_FN, FN_IP4_7_4, }

		GP_2_0_FN, FN_IP4_7_4, ))

	},

	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {

	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(

		0, 0,

		0, 0,

		GP_3_29_FN, FN_IP10_19_16,
@@ -2675,9 +2675,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_3_3_FN, FN_IP8_19_16,

		GP_3_2_FN, FN_IP8_15_12,

		GP_3_1_FN, FN_IP8_11_8,

		GP_3_0_FN, FN_IP8_7_4, }

		GP_3_0_FN, FN_IP8_7_4, ))

	},

	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {

	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,
@@ -2709,9 +2709,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_4_3_FN, FN_IP11_3_0,

		GP_4_2_FN, FN_IP10_31_28,

		GP_4_1_FN, FN_IP10_27_24,

		GP_4_0_FN, FN_IP10_23_20, }

		GP_4_0_FN, FN_IP10_23_20, ))

	},

	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {

	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(

		GP_5_31_FN, FN_IP17_27_24,

		GP_5_30_FN, FN_IP17_23_20,

		GP_5_29_FN, FN_IP17_19_16,
@@ -2743,7 +2743,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_5_3_FN, FN_IP14_11_8,

		GP_5_2_FN, FN_IP14_7_4,

		GP_5_1_FN, FN_IP14_3_0,

		GP_5_0_FN, FN_IP13_31_28, }

		GP_5_0_FN, FN_IP13_31_28, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,

			     4, 4, 4, 4, 4, 4, 4, 4) {

drivers/pinctrl/sh-pfc/pfc-r8a7778.c

+10 −10
Original line number Diff line number Diff line
@@ -2104,7 +2104,7 @@ static const struct sh_pfc_function pinmux_functions[] = { 
};



static const struct pinmux_cfg_reg pinmux_config_regs[] = {

	{ PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {

	{ PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP(

		GP_0_31_FN,	FN_IP1_14_11,

		GP_0_30_FN,	FN_IP1_10_8,

		GP_0_29_FN,	FN_IP1_7_5,
@@ -2136,9 +2136,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_0_3_FN,	FN_IP0_4_2,

		GP_0_2_FN,	FN_PENC1,

		GP_0_1_FN,	FN_PENC0,

		GP_0_0_FN,	FN_IP0_1_0 }

		GP_0_0_FN,	FN_IP0_1_0 ))

	},

	{ PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {

	{ PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP(

		GP_1_31_FN,	FN_IP4_6_4,

		GP_1_30_FN,	FN_IP4_3_1,

		GP_1_29_FN,	FN_IP4_0,
@@ -2170,9 +2170,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_1_3_FN,	FN_IP1_27_25,

		GP_1_2_FN,	FN_IP1_24,

		GP_1_1_FN,	FN_WE0,

		GP_1_0_FN,	FN_IP1_23_21 }

		GP_1_0_FN,	FN_IP1_23_21 ))

	},

	{ PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {

	{ PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP(

		GP_2_31_FN,	FN_IP6_7,

		GP_2_30_FN,	FN_IP6_6_5,

		GP_2_29_FN,	FN_IP6_4_2,
@@ -2204,9 +2204,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_2_3_FN,	FN_IP4_12_11,

		GP_2_2_FN,	FN_IP4_10_9,

		GP_2_1_FN,	FN_IP4_8,

		GP_2_0_FN,	FN_IP4_7 }

		GP_2_0_FN,	FN_IP4_7 ))

	},

	{ PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {

	{ PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP(

		GP_3_31_FN,	FN_IP8_10_9,

		GP_3_30_FN,	FN_IP8_8_6,

		GP_3_29_FN,	FN_IP8_5_3,
@@ -2238,9 +2238,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_3_3_FN,	FN_IP6_10,

		GP_3_2_FN,	FN_SSI_SCK34,

		GP_3_1_FN,	FN_IP6_9,

		GP_3_0_FN,	FN_IP6_8 }

		GP_3_0_FN,	FN_IP6_8 ))

	},

	{ PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {

	{ PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,
@@ -2272,7 +2272,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_4_3_FN,	FN_IP8_21_19,

		GP_4_2_FN,	FN_IP8_18_16,

		GP_4_1_FN,	FN_IP8_15_14,

		GP_4_0_FN,	FN_IP8_13_11 }

		GP_4_0_FN,	FN_IP8_13_11 ))

	},



	{ PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,

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