Commit 69e30028 authored Dec 21, 2019 by Grygorii Strashko Committed by Tero Kristo Jan 20, 2020

clk: ti: dra7: fix parent for gmac_clkctrl



The parent clk for gmac clk ctrl has to be gmac_main_clk (125MHz) instead
of dpll_gmac_ck (1GHz). This is caused incorrect CPSW MDIO operation.
Hence, fix it.

Fixes: dffa9051 ('clk: ti: dra7: add new clkctrl data')
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

parent 7dfd5e61

drivers/clk/ti/clk-7xx.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -428,7 +428,7 @@ static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
		};

		static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
		{ DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck" },
		{ DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "gmac_main_clk" },
		{ 0 },
		};

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