Commit 692ccce7 authored by Rob Herring's avatar Rob Herring Committed by Lorenzo Pieralisi
Browse files

PCI: dwc: tegra: Use pci_ops for root config space accessors 

Now that DWC drivers can setup their own pci_ops for the root and child
buses, convert the Tegra driver to use the standard pci_ops for root
bus config accesses.

Link: https://lore.kernel.org/r/20200821035420.380495-8-robh@kernel.org


Signed-off-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-tegra@vger.kernel.org
parent 10a797c6

drivers/pci/controller/dwc/pcie-tegra194.c

+16 −14
Original line number Diff line number Diff line
@@ -568,42 +568,44 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) 
	return IRQ_HANDLED;

}



static int tegra_pcie_dw_rd_own_conf(struct pcie_port *pp, int where, int size,

				     u32 *val)

static int tegra_pcie_dw_rd_own_conf(struct pci_bus *bus, u32 devfn, int where,

				     int size, u32 *val)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);



	/*

	 * This is an endpoint mode specific register happen to appear even

	 * when controller is operating in root port mode and system hangs

	 * when it is accessed with link being in ASPM-L1 state.

	 * So skip accessing it altogether

	 */

	if (where == PORT_LOGIC_MSIX_DOORBELL) {

	if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) {

		*val = 0x00000000;

		return PCIBIOS_SUCCESSFUL;

	}



	return dw_pcie_read(pci->dbi_base + where, size, val);

	return pci_generic_config_read(bus, devfn, where, size, val);

}



static int tegra_pcie_dw_wr_own_conf(struct pcie_port *pp, int where, int size,

				     u32 val)

static int tegra_pcie_dw_wr_own_conf(struct pci_bus *bus, u32 devfn, int where,

				     int size, u32 val)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);



	/*

	 * This is an endpoint mode specific register happen to appear even

	 * when controller is operating in root port mode and system hangs

	 * when it is accessed with link being in ASPM-L1 state.

	 * So skip accessing it altogether

	 */

	if (where == PORT_LOGIC_MSIX_DOORBELL)

	if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL)

		return PCIBIOS_SUCCESSFUL;



	return dw_pcie_write(pci->dbi_base + where, size, val);

	return pci_generic_config_write(bus, devfn, where, size, val);

}



static struct pci_ops tegra_pci_ops = {

	.map_bus = dw_pcie_own_conf_map_bus,

	.read = tegra_pcie_dw_rd_own_conf,

	.write = tegra_pcie_dw_wr_own_conf,

};



#if defined(CONFIG_PCIEASPM)

static void disable_aspm_l11(struct tegra_pcie_dw *pcie)

{
@@ -970,6 +972,8 @@ static int tegra_pcie_dw_host_init(struct pcie_port *pp) 
	struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);

	u32 val, tmp, offset, speed;



	pp->bridge->ops = &tegra_pci_ops;



	tegra_pcie_prepare_host(pp);



	if (dw_pcie_wait_for_link(pci)) {
@@ -1057,8 +1061,6 @@ static const struct dw_pcie_ops tegra_dw_pcie_ops = { 
};



static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = {

	.rd_own_conf = tegra_pcie_dw_rd_own_conf,

	.wr_own_conf = tegra_pcie_dw_wr_own_conf,

	.host_init = tegra_pcie_dw_host_init,

	.set_num_vectors = tegra_pcie_set_msi_vec_num,

};

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