Commit 10a797c6 authored by Rob Herring's avatar Rob Herring Committed by Lorenzo Pieralisi
Browse files

PCI: dwc: keystone: Use pci_ops for config space accessors 

Now that DWC drivers can setup their own pci_ops for the root and child
buses, convert the TI Keystone driver to use the standard pci_ops for
config accesses.

Link: https://lore.kernel.org/r/20200821035420.380495-7-robh@kernel.org


Signed-off-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
parent fffbb0ba

drivers/pci/controller/dwc/pci-keystone.c

+18 −22
Original line number Diff line number Diff line
@@ -430,10 +430,10 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) 
	ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);

}



static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,

				 unsigned int devfn, int where, int size,

				 u32 *val)

static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus,

					   unsigned int devfn, int where)

{

	struct pcie_port *pp = bus->sysdata;

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);

	u32 reg;
@@ -444,25 +444,14 @@ static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, 
		reg |= CFG_TYPE1;

	ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg);



	return dw_pcie_read(pp->va_cfg0_base + where, size, val);

	return pp->va_cfg0_base + where;

}



static int ks_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,

				 unsigned int devfn, int where, int size,

				 u32 val)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);

	u32 reg;



	reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) |

		CFG_FUNC(PCI_FUNC(devfn));

	if (!pci_is_root_bus(bus->parent))

		reg |= CFG_TYPE1;

	ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg);



	return dw_pcie_write(pp->va_cfg0_base + where, size, val);

}

static struct pci_ops ks_child_pcie_ops = {

	.map_bus = ks_pcie_other_map_bus,

	.read = pci_generic_config_read,

	.write = pci_generic_config_write,

};



/**

 * ks_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
@@ -490,6 +479,12 @@ static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp) 
	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);

}



static struct pci_ops ks_pcie_ops = {

	.map_bus = dw_pcie_own_conf_map_bus,

	.read = pci_generic_config_read,

	.write = pci_generic_config_write,

};



/**

 * ks_pcie_link_up() - Check if link up

 */
@@ -807,6 +802,9 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) 
	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);

	int ret;



	pp->bridge->ops = &ks_pcie_ops;

	pp->bridge->child_ops = &ks_child_pcie_ops;



	ret = ks_pcie_config_legacy_irq(ks_pcie);

	if (ret)

		return ret;
@@ -842,8 +840,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) 
}



static const struct dw_pcie_host_ops ks_pcie_host_ops = {

	.rd_other_conf = ks_pcie_rd_other_conf,

	.wr_other_conf = ks_pcie_wr_other_conf,

	.host_init = ks_pcie_host_init,

	.msi_host_init = ks_pcie_msi_host_init,

	.scan_bus = ks_pcie_v3_65_scan_bus,

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