Commit 680e1af7 authored by Stanislav Lisovskiy's avatar Stanislav Lisovskiy Committed by Ville Syrjälä
Browse files

drm/i915: Add pre/post plane updates for SAGV 



Lets have a unified way to handle SAGV changes,
espoecially considering the upcoming Gen12 changes.

Current "standard" way of doing this in commit_tail
is pre/post plane updates, when everything which
has to be forbidden and not supported in new config
has to be restricted before update and relaxed after
plane update.

v2: - Removed unneeded returns(Ville)

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200415143911.10244-5-stanislav.lisovskiy@intel.com
parent a389c49f

drivers/gpu/drm/i915/display/intel_display.c

+4 −9
Original line number Diff line number Diff line
@@ -15354,12 +15354,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) 














		intel_set_cdclk_pre_plane_update(state);



























		/*













		 * SKL workaround: bspec recommends we disable the SAGV when we













		 * have more then one pipe enabled













		 */













		if (!intel_can_enable_sagv(state))













			intel_disable_sagv(dev_priv);













		intel_sagv_pre_plane_update(state);





























		intel_modeset_verify_disabled(dev_priv, state);















	}










@@ -15456,11 +15451,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)













	intel_check_cpu_fifo_underruns(dev_priv);















	intel_check_pch_fifo_underruns(dev_priv);



























	if (state->modeset)













	if (state->modeset) {















		intel_verify_planes(state);



























	if (state->modeset && intel_can_enable_sagv(state))













		intel_enable_sagv(dev_priv);













		intel_sagv_post_plane_update(state);













	}





























	drm_atomic_helper_commit_hw_done(&state->base);















































drivers/gpu/drm/i915/intel_pm.c



+16
−0






























Original line number
Diff line number
Diff line








@@ -3757,6 +3757,22 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)













	return 0;















}





























void intel_sagv_pre_plane_update(struct intel_atomic_state *state)













{













	struct drm_i915_private *dev_priv = to_i915(state->base.dev);



























	if (!intel_can_enable_sagv(state))













		intel_disable_sagv(dev_priv);













}



























void intel_sagv_post_plane_update(struct intel_atomic_state *state)













{













	struct drm_i915_private *dev_priv = to_i915(state->base.dev);



























	if (intel_can_enable_sagv(state))













		intel_enable_sagv(dev_priv);













}





























static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)















{















	struct drm_device *dev = crtc_state->uapi.crtc->dev;

































drivers/gpu/drm/i915/intel_pm.h



+2
−0






























Original line number
Diff line number
Diff line








@@ -44,6 +44,8 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv);













bool intel_can_enable_sagv(struct intel_atomic_state *state);















int intel_enable_sagv(struct drm_i915_private *dev_priv);















int intel_disable_sagv(struct drm_i915_private *dev_priv);













void intel_sagv_pre_plane_update(struct intel_atomic_state *state);













void intel_sagv_post_plane_update(struct intel_atomic_state *state);















bool skl_wm_level_equals(const struct skl_wm_level *l1,















			 const struct skl_wm_level *l2);















bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,



































































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