Commit a389c49f authored by Stanislav Lisovskiy's avatar Stanislav Lisovskiy Committed by Ville Syrjälä
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drm/i915: Prepare to extract gen specific functions from intel_can_enable_sagv 



Addressing one of the comments, recommending to extract platform
specific code from intel_can_enable_sagv as a preparation, before
we are going to add support for tgl+.

v2: - Removed whitespace
v3: - Removed premature debug and new cycle introduction(Ville)
    - Added missing no active pipes check(Ville)
v4: - Fixed stupid mistake with plane_state caused by stupid macro change

Signed-off-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200415145740.28241-1-stanislav.lisovskiy@intel.com
parent 442e7ee8

drivers/gpu/drm/i915/intel_pm.c

+36 −25
Original line number Diff line number Diff line
@@ -3757,42 +3757,22 @@ intel_disable_sagv(struct drm_i915_private *dev_priv) 
	return 0;

}



bool intel_can_enable_sagv(struct intel_atomic_state *state)

static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)

{

	struct drm_device *dev = state->base.dev;

	struct drm_device *dev = crtc_state->uapi.crtc->dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_crtc *crtc;

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct intel_plane *plane;

	struct intel_crtc_state *crtc_state;

	enum pipe pipe;

	int level, latency;



	if (!intel_has_sagv(dev_priv))

		return false;



	/*

	 * If there are no active CRTCs, no additional checks need be performed

	 */

	if (hweight8(state->active_pipes) == 0)

	if (!crtc_state->hw.active)

		return true;



	/*

	 * SKL+ workaround: bspec recommends we disable SAGV when we have

	 * more then one pipe enabled

	 */

	if (hweight8(state->active_pipes) > 1)

		return false;



	/* Since we're now guaranteed to only have one active CRTC... */

	pipe = ffs(state->active_pipes) - 1;

	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

	crtc_state = to_intel_crtc_state(crtc->base.state);



	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)

		return false;



	for_each_intel_plane_on_crtc(dev, crtc, plane) {

		struct skl_plane_wm *wm =

		const struct skl_plane_wm *wm =

			&crtc_state->wm.skl.optimal.planes[plane->id];



		/* Skip this plane if it's not enabled */
@@ -3823,6 +3803,37 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state) 
	return true;

}



bool intel_can_enable_sagv(struct intel_atomic_state *state)

{

	struct drm_i915_private *dev_priv = to_i915(state->base.dev);

	struct intel_crtc *crtc;

	const struct intel_crtc_state *crtc_state;

	enum pipe pipe;



	if (!intel_has_sagv(dev_priv))

		return false;



	/*

	 * If there are no active CRTCs, no additional checks need be performed

	 */

	if (hweight8(state->active_pipes) == 0)

		return true;



	/*

	 * SKL+ workaround: bspec recommends we disable SAGV when we have

	 * more then one pipe enabled

	 */

	if (hweight8(state->active_pipes) > 1)

		return false;



	/* Since we're now guaranteed to only have one active CRTC... */

	pipe = ffs(state->active_pipes) - 1;

	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

	crtc_state = to_intel_crtc_state(crtc->base.state);



	return intel_crtc_can_enable_sagv(crtc_state);

}



/*

 * Calculate initial DBuf slice offset, based on slice size

 * and mask(i.e if slice size is 1024 and second slice is enabled

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