Commit 67ee606a authored Dec 08, 2018 by Jernej Skrabec Committed by Stephen Boyd Dec 10, 2018

clk: sunxi-ng: a64: Allow parent change for VE clock



Cedrus driver wants to set VE clock higher than it's possible without
changing parent rate.

Allow changing parent rate for VE clock, so clock rate can be set
freely.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

parent a41f85b6

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -570,7 +570,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
		0x134, 0, 5, 8, 3, BIT(15), 0);

		static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
		0x13c, 16, 3, BIT(31), 0);
		0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);

		static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
		0x140, BIT(31), CLK_SET_RATE_PARENT);

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