Commit a41f85b6 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-4.21' of... 

Merge tag 'sunxi-clk-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clock changes from Maxime Ripard:

 - Sigma Delta modulation for the A33 audio clocks
 - Support for the F1c100s SoC
 - Rework of the oscillator tree
 - H6 display engine clocks

* tag 'sunxi-clk-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks
  clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL
  clk: sunxi-ng: h3: Allow parent change for ve clock
  clk: sunxi-ng: add support for suniv F1C100s SoC
  dt-bindings: clock: Add Allwinner suniv F1C100s CCU
  clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent
  clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output
  clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL
  clk: sunxi-ng: a64: Fix gate bit of DSI DPHY
  clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I
  clk: sunxi-ng: Add support for H6 DE3 clocks
  dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description
  clk: sunxi-ng: h6: Set video PLLs limits
  clk: sunxi-ng: Use u64 for calculation of NM rate
  clk: sunxi-ng: Adjust MP clock parent rate when allowed
  clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width
  clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock
parents 65102238 6e6da203

Documentation/devicetree/bindings/clock/sun8i-de2.txt

+3 −2
Original line number Diff line number Diff line 
Allwinner Display Engine 2.0 Clock Control Binding

--------------------------------------------------

Allwinner Display Engine 2.0/3.0 Clock Control Binding

------------------------------------------------------



Required properties :

- compatible: must contain one of the following compatibles:
@@ -8,6 +8,7 @@ Required properties : 
		- "allwinner,sun8i-v3s-de2-clk"

		- "allwinner,sun50i-a64-de2-clk"

		- "allwinner,sun50i-h5-de2-clk"

		- "allwinner,sun50i-h6-de3-clk"



- reg: Must contain the registers base address and length

- clocks: phandle to the clocks feeding the display engine subsystem.

Documentation/devicetree/bindings/clock/sunxi-ccu.txt

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ Required properties : 
		- "allwinner,sun50i-h5-ccu"

		- "allwinner,sun50i-h6-ccu"

		- "allwinner,sun50i-h6-r-ccu"

		- "allwinner,suniv-f1c100s-ccu"

		- "nextthing,gr8-ccu"



- reg: Must contain the registers base address and length

drivers/clk/sunxi-ng/Kconfig

+6 −0
Original line number Diff line number Diff line
@@ -6,6 +6,11 @@ config SUNXI_CCU 


if SUNXI_CCU



config SUNIV_F1C100S_CCU

	bool "Support for the Allwinner newer F1C100s CCU"

	default MACH_SUNIV

	depends on MACH_SUNIV || COMPILE_TEST



config SUN50I_A64_CCU

	bool "Support for the Allwinner A64 CCU"

	default ARM64 && ARCH_SUNXI
@@ -63,6 +68,7 @@ config SUN8I_V3S_CCU 


config SUN8I_DE2_CCU

	bool "Support for the Allwinner SoCs DE2 CCU"

	default MACH_SUN8I || (ARM64 && ARCH_SUNXI)



config SUN8I_R40_CCU

	bool "Support for the Allwinner R40 CCU"

drivers/clk/sunxi-ng/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ obj-y += ccu_nm.o 
obj-y				+= ccu_mp.o



# SoC support

obj-$(CONFIG_SUNIV_F1C100S_CCU)	+= ccu-suniv-f1c100s.o

obj-$(CONFIG_SUN50I_A64_CCU)	+= ccu-sun50i-a64.o

obj-$(CONFIG_SUN50I_H6_CCU)	+= ccu-sun50i-h6.o

obj-$(CONFIG_SUN50I_H6_R_CCU)	+= ccu-sun50i-h6-r.o

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

+31 −15
Original line number Diff line number Diff line
@@ -51,15 +51,26 @@ static struct ccu_nkmp pll_cpux_clk = { 
 * the base (2x, 4x and 8x), and one variable divider (the one true

 * pll audio).

 *

 * We don't have any need for the variable divider for now, so we just

 * hardcode it to match with the clock names

 * With sigma-delta modulation for fractional-N on the audio PLL,

 * we have to use specific dividers. This means the variable divider

 * can no longer be used, as the audio codec requests the exact clock

 * rates we support through this mechanism. So we now hard code the

 * variable divider to 1. This means the clock rates will no longer

 * match the clock names.

 */

#define SUN50I_A64_PLL_AUDIO_REG	0x008



static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",

static struct ccu_sdm_setting pll_audio_sdm_table[] = {

	{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },

	{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },

};



static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",

				       "osc24M", 0x008,

				       8, 7,	/* N */

				       0, 5,	/* M */

				       pll_audio_sdm_table, BIT(24),

				       0x284, BIT(31),

				       BIT(31),	/* gate */

				       BIT(28),	/* lock */

				       CLK_SET_RATE_UNGATE);
@@ -162,7 +173,12 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", 
#define SUN50I_A64_PLL_MIPI_REG		0x040



static struct ccu_nkm pll_mipi_clk = {

	.enable		= BIT(31),

	/*

	 * The bit 23 and 22 are called "LDO{1,2}_EN" on the SoC's

	 * user manual, and by experiments the PLL doesn't work without

	 * these bits toggled.

	 */

	.enable		= BIT(31) | BIT(23) | BIT(22),

	.lock		= BIT(28),

	.n		= _SUNXI_CCU_MULT(8, 4),

	.k		= _SUNXI_CCU_MULT_MIN(4, 2, 2),
@@ -581,7 +597,7 @@ static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" }; 
static const u8 dsi_dphy_table[] = { 0, 2, };

static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",

				       dsi_dphy_parents, dsi_dphy_table,

				       0x168, 0, 4, 8, 2, BIT(31), CLK_SET_RATE_PARENT);

				       0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);



static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",

			     0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
@@ -589,9 +605,9 @@ static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", 
/* Fixed Factor clocks */

static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);



/* We hardcode the divider to 4 for now */

/* We hardcode the divider to 1 for now */

static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",

			"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);

			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);

static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",

			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);

static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
@@ -911,10 +927,10 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev) 
	if (IS_ERR(reg))

		return PTR_ERR(reg);



	/* Force the PLL-Audio-1x divider to 4 */

	/* Force the PLL-Audio-1x divider to 1 */

	val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);

	val &= ~GENMASK(19, 16);

	writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);

	writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);



	writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);

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